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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.6

16-Jun-2023

CFR0011-120-00

24 of 55

when not set to be driven from GPIO_1 or GPIO_0.

10.2.1.2

SLEEP Enable

In order to reduce power consumption to a minimum, the host processor can send DA9313 into

SLEEP Mode. SLEEP mode is a configurable mode with configuration via the SLEEP_CTRL register.

This function is available in ACTIVE Mode and SLEEP mode when VDDIO_EN bit is high.

Any GPI pin can be configured as SLEEP_EN via the GPIO_1_PIN and GPIO_0_PIN bits. The

SLEEP_EN pin controls the SLEEP status bit in the MODE_CTRL register allowing read-back of the

current setting. The SLEEP bit can also be controlled over I2C when not set to be driven from GPI,

see section 11.4.

10.2.1.3

Power Cycle

The power cycle (PWC) input allows the host to perform a power cycle of DA9313 with OTP reload.

This function is provided in ACTIVE Mode and SLEEP Mode when VDDIO_EN bit is high.

Any GPI pin can be configured as PWC via the GPIO_1_PIN and GPIO_0_PIN bits. After PWC

assertion DA9313 de-asserts the power good (PG) pin for 10 µs and then initiates a power cycle.

The GPI_RESET bit is set in the FAULT_LOG for host read-back following power cycle back to

ACTIVE mode.

10.2.1.4

Clock Input

GPIO_1 supports the connection of an external oscillator delivering the target 6 MHz, see Table 6, to

the system. This requires that GPIO_1 is selected for external clock input (Ext_Clk_Inp) via

GPIO_1_PIN. The GPI does not generate any event in this case.

The switch over from the internal to external clock occurs on the falling edge of the clock. If the

external clock is not present, a clock detect switches control to the internal clock. In this case, I2C

communication is possible.

CAUTION

Removing an external clock without first reverting the internal clocking GPI setting may damage the device.

10.2.1.5

Output Ports

Output ports (GPOs) are supplied from the internal rail (VCORE or VDDIO) and can be configured to

be open drain or push-pull (selected via GPIO_1_MODE or GPIO_0_MODE). If a GPO is used as a

push-pull driver VDDIO has to be enabled. GPOs can also be supplied from an external rail by

disabling the internal 20

kΩ pull-up resistor in open-drain mode.

If the output ports are defined as general purpose outputs (GPOs), the low/high level is defined in

(PG), defined by GPIO_1_PIN and GPIO_0_PIN, the GPIO_1_TYPE or GPIO_0_TYPE fields

indicates the active low/high characteristics.

NOTE

In master/slave mode, with GPIO_1 operating in open drain with an external pull-up, the pull-up resistor must

be > 820

kΩ to prevent a false SLAVE_ID recognition.

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