DA9313 datasheet(25/55 Pages) RENESAS

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DA9313

High Efficiency Dual Cell Switched Capacitor Divider

Datasheet

Revision 3.6

16-Jun-2023

CFR0011-120-00

25 of 55

10.2.1.6

Power Good Indication

Power good (PG) voltage monitoring at the PVC output can be enabled. The PG function monitors

the VOUT rail and informs the host processor about a power cycle in advance of the power cycle

occurring. PG indication is selected via GPIO_1_PIN or GPIO_0_PIN .

The voltage monitoring threshold can be configured between 2.5 V and 5 V in 100 mV steps via

PVC_PG_ADJ. When the voltage drops below the VTH_PG_PVC threshold, the event E_PVC_PG is

generated and the PG pin is de-asserted. Active level is configurable via GPIO_0_TYPE.

After an under voltage condition has been triggered, the indicator will return back to PG after the

output voltage has recovered above VTH_PG_PVC + VHYS_PG_PVC, see Table 5.

When a power cycle is initiated the PG will be always be de-asserted for 10 µs in advance of the

power cycle occurring before exiting ACTIVE or SLEEP mode.

10.2.1.7

nIRQ

GPIO_0 and GPIO_1 both support an nIRQ function that indicates that an interrupt causing event

has occurred. The related event and status information, such as warnings about temperature and

voltages, over-current fault conditions or status changes at GPI ports, is available in the EVENT and

STATUS registers.

The nIRQ output is enabled via GPIO_1_PIN or GPIO_0_PIN.

nIRQ can be push-pull or open drain, selected via GPIO_1_TYPE or GPIO_0_TYPE, and can be

active LOW or active HIGH.

The EVENT registers hold information about the events that have occurred. Events are triggered by

a status change at the monitored signals. When an event bit is set the nIRQ signal is asserted,

unless this interrupt is masked by the appropriate in MASK register.

The masked bits only mask the nIRQ assertion, and do not suppress the event generation. The nIRQ

is not released until all event bits are cleared by writing a 1 to the appropriate EVENT register bits.

New events which have occurred during the reading of the EVENT register are held until the register

has been cleared; ensuring that host processor does not miss them.

10.2.2

nONKEY

The nONKEY pin can be configured via the NONKEY_MODE register. It can operate as a user

power button or as a level sensitive IC_EN pin, which allows the DA9313 state to be controlled from

the GPO of another device.

The nONKEY input port is always enabled to ensure that activities which should generate an

application wake-up or power down are always captured. The level of the debounced signal is

provided by the status flag nONKEY.

NOTE

The nONKEY port should be never externally overdriven to a voltage higher than VCORE.

10.2.2.1

Event Generation

In ACTIVE or SLEEP modes a press of nONKEY causes an IRQ assertion if not suppressed via the

interrupt mask M_nONKEY.

The event can be generated from either the rising or the falling edge of the nONKEY pin via

NONKEY_PIN setting:

0: An E_nONKEY event is generated when the debounced signal from port nONKEY goes low

(asserting edge). If not masked, an interrupt is signaled to the host via nIRQ.

1: An E_nONKEY event is generated when the debounced signal from port nONKEY goes high (de

asserting edge). If not masked, an interrupt is signaled to the host via nIRQ.

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