VDD1

VDD2

PTT

PH

SCR_TST

To rectifier ground

To rectifier

supply

To the 200-turn coil

To the 100-turn coil

SW_OPEN

GND

To HOT

VIA to Analog

Ground Plane

VIA to Analog

Ground Plane

To R11

VIAs to tie thermal

pad to ground

plane

C8

To

Q1

To

R9

To

R10

SEL

To

button

R5

R12

C2

R5

C1

R4

R3

C5

C4

R7

R6

C6

Bottom or

mid-layer

trace

Bottom or

mid-layer

trace

24

AFE3010

SBFS042 – JUNE 2020

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10 Layout

10.1 Layout Guidelines

The layout of the AFE3010 and its surrounding circuit is critical to maintaining performance and minimizing

unwanted noise coupling. Follow these layout guidelines:

•

Place all capacitors as close as possible to their respective pins or nodes.

•

Route the signal traces from the 1000-turn coil to the amplifier as a differential pair.

•

Provide low-impedance ground connections throughout the board, especially between the ground pin of the

rectifier (D1) and the ground pin of the AFE3010.

•

Connect the bottom AFE3010 thermal pad to board ground to help with noise immunity.

10.2 Layout Example

Figure 21. AFE3010 Layout Example