AFE4403 datasheet(69/85 Pages) TI2

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AFE4404

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SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

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Typical Application (continued)

Figure 92 illustrates the typical connection of the AFE. The following points are to be noted:

1. Use decoupling capacitors (1 µF or higher) placed close to the device to filter noise on RX_SUP and

TX_SUP.

2. The voltage level used for IO_SUP must be the same as the I/O voltage level for the MCU.

3. In external clock mode, TI recommends connecting a series resistor (Rseries) on the CLK pin. At power-up

and before a RESET pulse is applied, the register bits can be in an uninitialized state. The CLK pin can

possibly be configured as an output pin in this uninitialized state because the CLK pin is an I/O pin. In such a

scenario, Rseries limits the current (because the MCU also attempts to drive the CLK pin). For maximum

frequency of the external clock (60 MHz), the Rseries value is recommended to be 500 Ω.

4. In internal oscillator mode, a shunt resistor (Rshunt) equal to 500 kΩ is recommended to be connected to the

CLK pin. At power-up and after reset, the device resets to the default mode of the external clock. The CLK

pin is in a tri-state mode until the internal clock mode with the CLK output enabled is written through the I2C

interface. The function of Rshunt is to pull down the CLK pin to a logic level of 0 so that the input clock to the

MCU is at a logic level even when the CLK pin is tri-stated.

5. When in power-down mode (PWDN and PDNAFE) the CLK pin must be shut off (tri-stated or driven to zero),

if externally driven.

9.2.1 Design Requirements

The AFE architecture is very flexible, and can be used for both high-performance saturation of peripheral

capillary oxygen (SpO2) applications as well as low-power, battery-operated heart-rate monitoring (HRM)

applications as a result of this flexibility. The high dynamic range of the AFE enables excellent SNR for the signal

of interest (usually small in amplitude) even in the presence of large-signal artifacts resulting from ambient and

motion changes.

9.2.2 Detailed Design Procedure

The following important factors are key to extracting the full performance benefit from the AFE:

1. Good optics including bright LEDs and high-sensitivity photodiodes

2. Good mechanical design

3. A calibration loop that sets the optimal AFE settings based on the signal conditions

TI recommends that a system-level budgeting of dynamic range be initially done based on the following factors:

1. The range of the dc signal currents that are input to the AFE

2. The range of ac-to-dc ratio across different users

3. Signal current changes expected from artifacts (such as motion and ambient light changes)

4. The SNR required for heart-rate extraction algorithms to function successfully

Based on the above analysis, the available dynamic range from the AFE (approximately 100 dB) can be

partitioned between the various components, and the target dc level for the calibration algorithm can also be

arrived at.

9.2.2.1 System-Level ESD Considerations

To meet system-level ESD requirements, additional on-board ESD protection diodes may be required to be

connected to the AFE4404 input pins. The input pins are sensitive to leakage, so using low-leakage ESD diodes

is recommended for protecting these pins.

TI’s portfolio of ESD protection devices can be accessed at the Overview for ESD Protection Diodes page.

The ESD Protection Layout Guide (SLVA680) is available for download at www.ti.com.

AFE4403 Datasheet(PDF) 69 Page - Texas Instruments

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