AFE4403 datasheet(71/85 Pages) TI2

71 / 85 page

Sample Number

200

400

600

800

1000

435000

436000

437000

438000

439000

440000

441000

442000

443000

444000

445000

446000

447000

AFE4404

www.ti.com

SBAS689D – JUNE 2015 – REVISED DECEMBER 2016

Product Folder Links: AFE4404

Submit Documentation Feedback

Typical Application (continued)

Figure 95. (LED-Ambient) Data with an Optimal AFE Setting

9.2.3 Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

Figure 1 illustrates the receiver current across different external clock frequencies. Each of the curves

corresponds to a different CLKDIV_EXTMODE setting that determines the division ratio between the external

clock and the internal clock (CLK_INT). The internal clock frequency must be in the range of 4 MHz to 6 MHz for

proper operation, and each curve corresponds to a sweep of the external clock frequency that corresponds to an

internal clock frequency sweep over the range of 4 MHz to 6 MHz.

Figure 2 illustrates the receiver current across the PRF with the dynamic power-down signal (PDN_CYCLE)

enabled during the portion of the period when the receiver does not need to be active. The active period is

maintained as 500 µs for each PRF setting and the device is in power-down mode (set by PDN_CYCLE) for the

rest of the period. Additionally, the timing margins indicated as t8 and t9 in Figure 35 are included before and

after the PDN_CYCLE pulse. The fraction of time that the device is in power-down mode over a period increases

with reduction in the PRF because the period scales inversely with PRF. This timing is the reason why the curve

displays a reduction in the average receiver current with reduction in PRF. The curve corresponding to

CLKDIV_PRF = 1 terminates at a lower PRF of approximately 61 Hz, which is determined by the maximum

range of the 16-bit timing counter (4 MHz divided by 216). With the CLKDIV_PRF set to 16, the timer clock is

divided by 16. Thus, the lower PRF range can be extended down to a few hertz (the recommended operation is

to restrict the range to 10 Hz or higher). For the same PRF (for example 100 Hz), a higher CLKDIV_PRF setting

results in a lower power consumption because the timer engine runs on a slower clock and takes less switching

current.

The noise plots from Figure 3 to Figure 7 are taken at a PRF of 100 Hz. For this PRF setting, the noise at the

output of the AFE is distributed from 0 Hz to 50 Hz. Plots that indicate the noise as over Nyquist bandwidth have

integrated noise from 1 Hz to 50 Hz. The plots that indicate the noise as over 20-Hz bandwidth have integrated

noise until 20 Hz. These plots are suitable for when additional low-pass filtering is implemented in the MCU to

limit the noise bandwidth (in this case, to 20 Hz). This low-pass filtering can improve SNR because the PPG

signal has information contained in the frequency band below 10 Hz.

Figure 3 illustrates the input-referred noise current versus sampling duration duty cycle for different voltage levels

at the receiver output. The PPG signal has a dc component that can cause the signal at the output of the

receiver to be anywhere between ±FS (full-scale). The curves in Figure 3 illustrate a slight increase in the noise

around higher dc levels, which results from additional noise sources in the ADC. The input-referred noise current

can be visualized as a noise current flowing into one of the input pins (for instance, INP) and flowing out of the

other (for example, INM). The noise is computed on the samples that constitute the difference between the LED

phase and the ambient phase.

AFE4403 Datasheet(PDF) 71 Page - Texas Instruments

AFE4403 Datasheet(HTML) 71 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL