| Electronic Components Datasheet Search |
|
LM98519 Datasheet(PDF) 28 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
LM98519 Datasheet(HTML) 28 Page - Texas Instruments |
|
28 / 59 page ![]() LM98519 SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014 www.ti.com Device Functional Modes (continued) 7.4.2 AFEPHASEn Details for SAMPLE and HOLD Input Mode In Sample/Hold mode, the SAMPLE and HOLD inputs are used. The rising edge of SAMPLE defines the start of the sample control pulse, and the rising edge of HOLD defines the end of the sample control pulse. This sample control pulse is then gated by the low period of the AFEPHASEn signal to generate the resulting SAMPLE signal used internally. The AFEPHASEn signal which has the low period overlapping the sample control pulse will give the best performance. 7.4.3 AFEPHASEn: 6 Channel and 3 Channel Modes In 6 Channel Mode, there are two full cycles of MCLK and ADCCLK for each sensor pixel period. This allows the two AFE channels to be multiplexed into the single ADC. In this mode, there are 4 possible AFEPHASEn timings available. In 3 Channel Mode, there is only one cycle of MCLK and ADCCLK per pixel period. Because of this, there are only 2 choices for AFEPHASEn, as shown in Figure 21 through Figure 23. 7.4.4 LM98519 AFEPHASE Synchronization There are three main modes of operation for the LM98519 1. 6 channel mode using ADC Rate MCLK – Clock Doubler is bypassed 2. 6 channel mode using Pixel Rate MCLK – Clock Doubler is used 3. 3 channel mode using Pixel Rate MCLK – Clock Doubler is bypassed In case #1, where an ADC rate (2x of pixel rate) clock is input, the LM98519 needs one additional signal to ensure synchronization between the internal sampling phases and the pixel rate input signal. This synchronization is done using the CLPIN input signal in combination with MCLK. The CLPIN input generates an internal reset signal that sets the internal AFEPHASE state machine into a known relationship with MCLK and CLPIN. This ensures the AFEPHASE sampling is synchronized to the host sensor timing. Figure 21 through Figure 23 indicate the phase relationship between MCLK and AFEPHASE when CLPIN is used for synchronization. 28 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated Product Folder Links: LM98519 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |