LM98519 datasheet(39/59 Pages) TI2

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SENB

SCLK

SDI

SDO

SENW

SENSC

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2

A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

HiZ

LM98519

www.ti.com

SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014

7.5.9 Serial Interface

The serial control interface is based on the common microwire interface with a few specific timing details, as

shown below. Bits A5, A4, A3, A2, A1, A0 select the configuration register currently being written to or read

within the flat register space.

NOTE

The serial interface is initially configured to work in the absence of MCLK. Once MCLK is

established, the configuration can be changed to work with MCLK. This is done by setting

the Serial Interface Mode bit in Register 0x01, bit 3 = 1. Operation with MCLK will reduce

any timing restrictions required in the non-MCLK mode. In addition, the Auto Clear of AGC

Status will only work in MCLK Present mode.

7.5.10 Serial Write

Figure 33. Serial Write

•

The positive edge of SCLK is used to receive data on SDI.

•

Last 15 bits of data before SEN toggled high will be loaded into AFE.

•

A command whose length is less than 15 bits will be discarded.

•

SDO will be Hi-Z during write operation.

•

At the second cycle shown above, either read or write command is possible.

•

The MODE bit must be “0” when writing to registers.

•

A Write command consists of one MODE bit, 6 address bits and 8 data bits.

•

While SEN is high, the AFE will accept either high or low with respect to SCLK and SDI.

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