LM98519 datasheet(34/59 Pages) TI2

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LM98519

SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014

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Programming (continued)

In addition, the following registers should be initialized before starting the loop:

Table 5. Initialize Registers Before Loop

FUNCTION

PK_DET_ST

Start of the white pixel averaging in pixels from rising edge of CLPIN or BLKCLP

(0x2Ah, 0x2Bh)

PK_DET_WID

Number of pixels in each line over which white pixels are averaged

(0x2Ch, 0x2Dh)

AGCDuration

Duration in number of lines the loop should run. If set to 0, the loop will not run. Valid settings are 1 to 255.

(0x2Eh)

AGCTarget

AGC target, between 512 to 1023

(0x2Fh, 0x30h)

AGCTolerance

Allowed error margin from the target value

(0x31h)

AGC_BLKINT

Black Offset Integration, if used

(0x32h)

AGC_CONFIG

Select reference edge CLPIN or BLKCLP rising edge, Enable/Disable

(0x28h)

AGC_ONB Pin, Incremental Search Enable, Black Offset Enable

After all registers are initialized, the AGC_ON bit (0x28h, b0) can be set, or the AGC_ONB pin can be pulsed to

start the white loop.

7.5.2 Sample Timing Control

Sample timing is controlled through the combination of the selected internal AFEPHASEn signal, and one or

several user inputs.

The input timing control pins can operate in two different modes:

SAMPLE and HOLD (Used with S/H mode sampling only)

In this mode, the rising edge of the SAMPLE signal controls the start of the sampling, while the rising edge of

HOLD stops sampling and holds the signal. This mode cannot be used with CDS operation.

SHP and SHD (Used with CDS and S/H modes of sampling)

In this mode, the SHP pulse is used to sample the reference level of the signal, while the SHD pulse is used to

sample the signal (brightness) information when CDS mode is used. If CDS is turned off, then SHD is used to

control the signal sample timing and SHP is not used.

The different input timing modes are selected by bits in Registers 0x00, 0x02, and 0x04, as shown in Table 6:

Table 6. Input Timing Modes

MODE

REG

DESCRIPTION

0x04[1]

0x02[7]

0x02[3:2]

0x02[1]

0x00[0]

SH3 (Default)

Sample and Hold mode, clocked by SAMPLE

and HOLD clocks(2)

SH2

Sample and Hold mode, clocked by SAMPLE

and HOLD clocks(3)

SH1a

Sample and Hold mode, clocked by

See(1)

AFEPHASE(3)

SH1b

Sample and Hold mode, clocked by SHD(3)

CDSa

CDS mode, sampled by AFEPHASE(3)

CDSb

CDS mode, sampled by SHP and SHD

clocks(3)

(1)

AFEPHASE bits should be set to “11” in SH3 mode (both 3ch and 6ch operation)

(2)

AFEPHASE is automatically set by the HOLD input timing. Only ADC Rate MCLK is allowed.

(3)

AFEPHASE is synchronized by MCLK and CLPIN inputs

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