LM98519 datasheet(46/59 Pages) TI2

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LM98519

SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014

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Table 10. Configuration Registers Details (continued)

ADDR

DEFAULT

DESCRIPTION

(HEX)

NAME

(HEX)

0x24

BLKCLP_CTRL1

0x84

Digital Black Level Clamp Control

•

[7:3] = Pixel Averaging o 00000 4 pixels o 00001 8 pixels

–

00010 12 pixels

–

00011 16 pixels

–

00100 20 pixels

–

00101 24 pixels

–

00110 28 pixels

–

10000 32 pixels

–

10001 64 pixels

–

10010 96 pixels

–

10011 128 pixels

–

10100 160 pixels

–

10101 192 pixels

–

10110 224 pixels

–

10111 256 pixels

–

11000 288 pixels

–

11001 320 pixels

–

11010 352 pixels

–

11011 384 pixels

–

11100 416 pixels

–

11101 448 pixels

–

11110 480 pixels

–

11111 512 pixels

–

other combinations are Reserved

•

[2:0] = Offset Integration

–

000:Divide-by-2

–

001:Divide-by-4

–

010:Divide-by-8

–

011:Divide-by-16

–

100:Divide-by-32

–

101:Divide-by-64

–

110:Divide-by-128

–

Reserved

0x25

CDAC_THLD_MSB

0x50

CDAC Threshold for BLK LP MSB Default value is 321d, so loop will change FDAC by 321

to compensate for change of 1 in CDAC.

To optimize even further, this can be changed to 314d.

If FDAC is set to the large range, then this value should be changed to 184d.

•

[7:0] = Threshold[9:2]

0x26

CDAC_THLD_LSB

0x40

CDAC Threshold for BLK LP LSB

•

[7:6] = Threshold[1:0]

•

[5:0] = Reserved. Set to 0.

0x27

High Speed Mode

0x88

•

[7:5] = High Speed Mode Hysteresis

•

[4:0] = High Speed Mode Threshold

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