LM98519 datasheet(8/59 Pages) TI2

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LM98519

SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014

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Electrical Characteristics (continued)

The following specifications apply for VDDA = VDDD = VDDO = 3.3 V; FMCLK = 65 Ms/s and TA =+25°C unless otherwise

noted. Boldface limits apply for TA = TMIN to TMAX. All other limits apply for TA =+25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET FDAC (±10 bits)

Large FDAC range

102

110.5

120

DAC Full Scale (input referred)

±mV

Small FDAC range

59.5

DAC Monotonicity

Monotonic

OFFSET CDAC (±4 bits)

DAC Full Scale (input referred)

255

277

300

±mV

DAC Monotonicity

Monotonic

LOGIC I/O DC PARAMETERS

Logic Input Voltage High

SHP, SHD, CLPIN, BLKCLP,

VIH

2.0

AGC_ONB, MCLK, SCLK, SDI,

SENB

Logic Input Voltage Low

SHP, SHD, CLPIN, BLKCLP,

VIL

0.8

AGC_ONB, MCLK, SCLK, SDI,

SENB

Excludes AGC_ONB, BLKCLP,

IIN

Logic Input Leakage

SENB, RESETB due to pull-ups or

–100

100

pull-downs on those pins

VDDD = 3.6 V, Iout = -0.5 mA

3.3

3.56

VOH

Logic Output Voltage High

VDDD = 3.0 V, Iout = -0.5 mA

2.7

2.9

VDDD = 3.6 V, Iout = 1.6 mA

0.11

0.2

VOL

Logic Output Voltage Low

VDDD = 3.0 V, Iout = 1.6 mA

0.11

0.2

VRES

Power On Reset Threshold

From simulation

1.18

1.5

AFE/ADC TIMING

6 channel mode

fMCLK

MCLK frequency

MHz

3 channel mode

32.5

MCLK Duty Cycle

45%

55%

6 Channel Mode

32.5

Input Sampling Rate

MS/s

3 Channel Mode

32.5

MCLK Present Mode

tMCLK

tRESET

RESETB Pulse Width

MCLK Idle Mode

MCLK Present Mode (ensured by

tMCLK

design)

tRESET_CLR RESETB Clear Time

MCLK Idle Mode (ensured by

design)

tSHD

SHP/SHD high period

Ensured by design

8.2

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