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LM98519 Datasheet(PDF) 49 Page - Texas Instruments |
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LM98519 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 59 page ![]() LM98519 www.ti.com SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Design Requirements See Figure 36 for an example circuit and the required minimum circuitry around the LM98519. All power supply voltages should be provided from clean linear regulator outputs, NOT switching power supplies. 8.2 Detailed Design Procedure 1. 3.3-V Power for Analog, Digital, and Outputs (VDDA, VDDD, and VDDO) supplies. It is recommended to use a common LDO regulator for al 3.3 V supplies, using EMI filter devices and dedicated coupling to isolate any noise between buses. 2. Input Timing Signals (Ground referenced logic signal with: 2.0 V < VHigh < 3.3 V) (a) MCLK: Continuous clock signal at pixel rate or ADC rate of LM98519 (b) CLPIN: Once per scan line signal used to control input clamp for DC restoration of AC coupled CCD input signals (c) BLKCLP: Once per scan line signal used to indicate beginning of black pixels for Black (Offset) Level Calibration (d) AGC_ONB – Input signal used to initiate start of White (Gain) Calibration (e) SHP/SAMPLE: Once per pixel signal used to control pixel sample timing (f) SHD/HOLD: Once per pixel signal used to control pixel sample timing 3. CCD signals at OS Inputs – These are connected to the outputs from the CCD sensor emitter follower buffer circuits. The signals are AC coupled to the AFE inputs using 0.1 uF capacitors. 4. Serial control interface from data processing module to LM98519 (Ground referenced logic signal with: 2.0 V < Vhigh < 3.3 V): (a) SENB – Serial enable to LM98519 (b) SCLK – Serial clock input to LM98519 (c) SDI – Data input to LM98519 (d) SDO – Data output from LM98519 5. Serialized data lines connected to FPGA or chip on data processing module 6. Adjust and reconfigure the configuration register settings as needed Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: LM98519 |
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