| Electronic Components Datasheet Search |
|
LM98519 Datasheet(PDF) 13 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
LM98519 Datasheet(HTML) 13 Page - Texas Instruments |
|
13 / 59 page ![]() MCLK DOUT t OD t OD Output data is updated on both edges of MCLK. Due to the internal timing delays in the LM98519, from MCLK to DOUT, the data can be safely latched using both edges of MCLK. MCLK t OD DOUT Output data is updated on the rising edge of MCLK. Data can be latched using the falling edge of MCLK. OSR1 OSG1 OSB1 SAMPLE HOLD MCLK DATA Pixel(n) Pixel(n+1) t AD t AD t SHD HOLD(n) t HMC t MCH t LAT t OD t MCLK t CH t CL Data(n) Data(n+1) Above timing relationships between SAMPLE, HOLD, and MCLK are for AEPHASE = X1. For other AEPHASE setting X0, the sampling timing can move earlier by ½ pixel period with respect to MCLK, but the latency as shown above will remain constant. LM98519 www.ti.com SNAS425C – OCTOBER 2007 – REVISED OCTOBER 2014 Figure 6. Output Latency and Timing – 3 Channel Mode Figure 7. Data Capture Timing – 6 Channel – ADC Rate MCLK Figure 8. Data Capture Timing – 6 Channel – Pixel Rate MCLK Copyright © 2007–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LM98519 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |