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ADC32RF44 Datasheet(PDF) 49 Page - Texas Instruments

Part # ADC32RF44
Description  ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter
PDF  128 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADC32RF44 Datasheet(HTML) 49 Page - Texas Instruments

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ADC32RF42
www.ti.com
SBAS844 – MAY 2017
Product Folder Links: ADC32RF42
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Copyright © 2017, Texas Instruments Incorporated
9.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
Table 20 lists the available JESD204B formats and valid ranges for the ADC32RF42 with decimation (dual-band
DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the maximum
ADC sample frequency. Table 21 shows the sample alignment on the different lanes.
Table 20. JESD Mode Options: Dual-Band Complex Output
DECIMATION
SETTING
(Complex)
NUMBER OF
ACTIVE DDCS
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
Divide-by-8
2 per channel
8
8
2
1
20x
1
0
0
2.5
4
8
4
1
40x
2
0
0
5
Divide-by-9
2 per channel
8
8
2
1
20x
1
0
0
2.22
4
8
4
1
40x
2
0
0
4.44
Divide-by-10
2 per channel
8
8
2
1
20x
1
0
0
2
4
8
4
1
40x
2
0
0
4
Divide-by-12
2 per channel
4
8
4
1
40x
2
0
0
3.33
Divide-by-16
2 per channel
4
8
4
1
40x
2
0
0
2.5
(1)
Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.
Table 21. JESD Sample Lane Assignment: Dual-Band Complex Output(1)
OUTPUT LANE
LMFS = 8821
LMFS = 4841
DA0
A10[15:8]
A10[7:0]
DA1
A1Q0[15:8]
A1Q0[7:0]
A1I0[15:8]
A1I0[7:0]
A1Q0[15:8]
A1Q0[7:0]
DA2
A2I0[15:8]
A2I0[7:0]
A2I0[15:8]
A2I0[7:0]
A2Q0[15:8]
A2Q0[7:0]
DA3
A2Q0[15:8]
A2Q0[7:0]
DB0
B1I0[15:8]
B1I0[7:0]
DB1
B1Q0[15:8]
B1Q0[7:0]
B1I0[15:8]
B1I0[7:0]
B1Q0[15:8]
B1Q0[7:0]
DB2
B2I0[15:8]
B2I0[7:0]
B2I0[15:8]
B2I0[7:0]
B2Q0[15:8]
B2Q0[7:0]
DB3
B2Q0[15:8]
B2Q0[7:0]



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