ADS5560 datasheet(34/62 Pages) TI2

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ADS5560, ADS5562

SLWS207B – MAY 2008 – REVISED JANUARY 2016

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Device Functional Modes (continued)

7.4.3.3 LVDS Buffer Internal Termination

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. These termination resistances are available: 325, 200, and 175

Ω (nominal with

±20% variation). Any combination of these three terminations can be programmed; the effective termination will

be the parallel combination of the selected resistances. This results in eight effective terminations from open (no

termination) to 75

Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signal

integrity. With 100-

Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved

(compared to no internal termination). The terminations can be controlled using the <DATA TERM> and

<CLKOUT TERM> register bits.

The voltage swing can be restored by using the LVDS current double mode (<CURR DOUBLE> register bit).

7.4.3.4 Parallel CMOS

In this mode, the digital data and output clock are put out as 3.3-V CMOS voltage levels. Each data bit and the

output clock is available on a separate pin in parallel. By default, the data outputs are valid during the rising edge

of the output clock. The output clock is CLKOUT.

7.4.3.5 Output Clock Position Programmability

In both the LVDS and CMOS modes, the output clock can be moved around the default position which occurs

using the SEN pin (as described in Table 6) or using the serial-interface <CLKOUT POSN> register bits

(Table 11).

7.4.4 Output Data Format

Two output data formats are supported: 2s-complement and offset binary. These formats can be selected using

the DFS pin or the serial-interface <DFS> register bit (see Table 9). In the event of an input voltage overdrive,

the digital outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0xFFFF in

offset binary output format, and 0x7FFF in 2s-complement output format. For a negative input overdrive, the

output code is 0x0000 in offset binary output format and 0x8000 in 2s complement output format.

7.4.5 Reference

The ADS556x device has a built-in internal reference that does not require external components. Design

schemes are used to linearize the converter load seen by the reference; this and the integration of the requisite

reference capacitors on-chip eliminates the need for external decoupling capacitors. The full-scale input range of

the converter can be controlled in the external reference mode as explained in the External Reference section.

The internal or external reference modes can be selected by controlling the MODE pin 23 (see Table 8 for

details) or by programming the serial-interface <REF> register bit.

7.4.5.1 Internal Reference

When the device is in internal reference mode, the REFP and REFM voltages are generated internally. The

common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog

input pins.

7.4.5.2 External Reference

When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the

VCM pin is buffered and gained internally, generating the REFP and REFM voltages. The differential input

voltage corresponding to full-scale is given by Equation 1. In this mode, the 1.5-V common-mode voltage to bias

the input pins must be generated externally.

Full-scale differential input volage, pp = (Voltage forced on VCM pin) × 2.67 × G

where

•

G = 10

–(Fine gain in db/20)

(1)

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