ADS5560 datasheet(12/62 Pages) TI2

12 / 62 page

ADS5560, ADS5562

SLWS207B – MAY 2008 – REVISED JANUARY 2016

www.ti.com

6.7 AC Electrical Characteristics for ADS5562, Fs = 80 MSPS

Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock

amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine

gain

(1). Minimum and maximum values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD = DRVDD

= 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FIN = 3 MHz

FIN = 10 MHz

83.8

LVDS interface

dBFS

FIN = 25 MHz

83.2

FIN = 30 MHz

82.8

SNR

Signal to noise ratio

FIN = 3 MHz

81.7

FIN = 10 MHz

81.4

CMOS interface

dBFS

FIN = 25 MHz

80.7

FIN = 30 MHz

80.4

RMS output noise

Inputs tied to common-mode

1.42

LSB

FIN = 3 MHz

80.5

FIN = 10 MHz

80.5

LVDS interface

dBFS

FIN = 25 MHz

79.5

SINAD

FIN = 30 MHz

Signal to noise and distortion

FIN = 3 MHz

80.5

ratio

FIN = 10 MHz

73.5

80.2

CMOS interface

dBFS

FIN = 25 MHz

79.3

FIN = 30 MHz

77.9

ENOB

LVDS interface, FIN = 10 MHz

12.2

13.1

bits

Effective number of bits

FIN = 3 MHz

FIN = 10 MHz

SFDR

dBc

Spurious free dynamic range

FIN = 25 MHz

FIN = 30 MHz

FIN = 3 MHz

FIN = 10 MHz

HD2

dBc

Second harmonic

FIN = 25 MHz

FIN = 30 MHz

(1)

After reset, the device is initialized to 1-dB fine gain setting. For SFDR and SNR performance across fine gains, see the Typical

Characteristics section.

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