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ADS5560 Datasheet(PDF) 13 Page - Texas Instruments

Part # ADS5560
Description  ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs
PDF  62 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS5560 Datasheet(HTML) 13 Page - Texas Instruments

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ADS5560, ADS5562
www.ti.com
SLWS207B – MAY 2008 – REVISED JANUARY 2016
6.8 Electrical Characteristics for ADS5562
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock
amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0 dB fine gain
(1), internal reference mode, DDR LVDS
interface. Minimum and maximum values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FIN = 3 MHz
85
FIN = 10 MHz
77
85
HD3
dBc
Third harmonic
FIN = 25 MHz
83
FIN = 30 MHz
80
FIN = 3 MHz
104
FIN = 10 MHz
102
Worst harmonic
dBc
other than HD2, HD3
FIN = 25 MHz
100
FIN = 30 MHz
100
FIN = 3 MHz
84
FIN = 10 MHz
75.5
83
THD
dBc
Total harmonic distortion
FIN = 25 MHz
82
FIN = 30 MHz
80
IMD
Two-tone intermodulation
FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS
92
dBFS
distortion
1
clock
Voltage overload recovery time
Recovery to 1% for 6-dB overload
cycles
(1)
After reset, the device is initialized to 1-dB fine gain setting. For SFDR and SNR performance across fine gains, see the Typical
Characteristics section.
6.9 Electrical Characteristics for ADS5560
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Maximum Rated, sine wave input clock, 1.5-VPP clock
amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine
gain
(1). Minimum and maximum values are across the full temperature range T
MIN = –40°C to TMAX = 85°C, AVDD = DRVDD
= 3.3 V, sampling rate = Maximum Rated, default fine gain (1 dB), unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FIN = 3 MHz
90
FIN = 10 MHz
78
88
HD3
dBc
Third harmonic
FIN = 25 MHz
83
FIN = 30 MHz
79
FIN = 3 MHz
104
FIN = 10 MHz
102
Worst harmonic
dBc
other than HD2, HD3
FIN = 25 MHz
101
FIN = 30 MHz
101
FIN = 3 MHz
88
FIN = 10 MHz
76.5
86
THD
dBc
Total harmonic distortion
FIN = 25 MHz
81
FIN = 30 MHz
78
IMD
Two-tone intermodulation
FIN1 = 5 MHz, FIN2 = 10 MHz, each tone –7 dBFS
98
dBFS
distortion
1
clock
Voltage overload recovery time
Recovery to 1% for 6-dB overload
cycles
(1)
After reset, the device is initialized to 1-dB fine gain setting. For SFDR and SNR performance across fine gains, see the Typical
Characteristics section.
Copyright © 2008–2016, Texas Instruments Incorporated
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Product Folder Links: ADS5560 ADS5562



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