ADS5560 datasheet(39/62 Pages) TI2

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RegisterData

(SCLK)

(DSU)

(DH)

(SLOADS)

SDATA

SCLK

SEN

RESET

(SLOADH)

ADS5560, ADS5562

www.ti.com

SLWS207B – MAY 2008 – REVISED JANUARY 2016

Figure 58. Serial Interface Timing Diagram

7.6 Register Maps

Table 9 gives a summary of all the modes that can be programmed through the serial interface.

Table 9. Summary of Functions Supported by Serial Interface(1) (2)

ADDRESS

IN HEX

A7 - A0

<LF NOISE

SUPPRESSION>

Output clock position programmability

<DF>

<STBY>

DATA FORMAT -

Global power

Enable low sampling

2s complement or

down

frequency operation

offset binary

<TEST PATTERN> – All 0s, all 1s, toggle,

ramp, custom pattern

<GAIN>

Fine gain 0 dB to 6 dB, in 1-dB steps

<CUSTOM A> Custom pattern (D7 TO D0)

<CUSTOM B> Custom pattern (D15 TO D8)

<ODI> Output data interface

DDR LVDS or parallel CMOS

<REF> Internal or

external reference

<RST>

Software reset

LVDS current

Internal termination – data outputs

Internal termination – output clock

programmability

LVDS current double

(1)

The unused bits in each register (shown by blank cells in above table) must be programmed as 0.

(2)

Multiple functions in a register can be programmed in a single write operation. See the Serial Interface section for details.

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