List of figures

VN7140AS12

4/39

DocID029756 Rev 2

List of figures

Figure 1: Block diagram ..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................14

Figure 5: Current sense accuracy versus IOUT .......................................................................................14

Figure 6: Switching time and pulse skew..................................................................................................15

Figure 7: Multisense timings (current sense mode)..................................................................................15

Figure 8: TDSTKON..................................................................................................................................16

Figure 9: Standby mode activation ...........................................................................................................17

Figure 10: Standby state diagram.............................................................................................................17

Figure 11: OFF-state output current .........................................................................................................17

Figure 12: Standby current .......................................................................................................................17

Figure 13: IGND(ON) vs. Tcase ...............................................................................................................18

Figure 14: Logic input high level voltage ..................................................................................................18

Figure 15: Logic input low level voltage....................................................................................................18

Figure 16: High level logic input current ...................................................................................................18

Figure 17: Low level logic input current ....................................................................................................18

Figure 18: Logic input hysteresis voltage .................................................................................................18

Figure 19: On-state resistance vs. Tcase .................................................................................................19

Figure 20: On-state resistance vs. VCC ...................................................................................................19

Figure 21: Turn-on voltage slope ..............................................................................................................19

Figure 22: Turn-off voltage slope ..............................................................................................................19

Figure 23: Won vs. Tcase .........................................................................................................................19

Figure 24: Woff vs. Tcase .........................................................................................................................19

Figure 25: ILIMH vs. Tcase.......................................................................................................................20

Figure 26: OFF-state open-load voltage detection threshold ...................................................................20

Figure 27: Vsense clamp vs. Tcase..........................................................................................................20

Figure 28: Vsenseh vs. Tcase ..................................................................................................................20

Figure 29: Undervoltage shutdown...........................................................................................................20

Figure 30: Application diagram .................................................................................................................22

Figure 31: Simplified internal structure .....................................................................................................22

Figure 32: Multisense and diagnostic

– block diagram.............................................................................24

Figure 33: Multisense block diagram ........................................................................................................25

Figure 34: Analogue HSD

– open-load detection in off-state ...................................................................26

Figure 35: Open-load / short to VCC condition.........................................................................................27

Figure 36: Maximum turn off current versus inductance ..........................................................................29

Figure 37: S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) ...........................................................30

Figure 38: SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) ..........................................................30

Figure 39: SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) ...........31

Figure 40: SO-8 thermal impedance junction ambient single pulse (one channel on) .............................31

Figure 41: Thermal fitting model of a double-channel HSD in SO-8 ........................................................32

Figure 42: SO-8 package outline ..............................................................................................................33

Figure 43: Reel for SO-8...........................................................................................................................34

Figure 44: SO-8 carrier tape .....................................................................................................................35

Figure 45: SO-8 schematic drawing of leader and trailer tape .................................................................36

Figure 46: SO-8 marking information........................................................................................................36