DAC53701 datasheet(26/59 Pages) TI2

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8.4 Device Functional Modes

8.4.1 Power Down Mode

The DACx3701 output amplifier and internal reference can be independently powered down through the

DAC_PDN bits (address D1h). At power up, the DAC output and the internal reference are disabled by default.

In power-down mode, the DAC output (OUT pin) is in a high-impedance state. To change this state to 10kΩ-

AGND (at power up), use the DAC_PDN bits (address D1h).

The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. Table

8-5 shows the DAC power-down bits.

Table 8-5. DAC Power-Down Bits

DAC_PDN[1]

DAC_PDN[0]

DESCRIPTION

D1h, GENERAL_CONFIG

Power up

Power down to 10 kΩ

Power down to high impedance (HiZ)

(default)

Power down to 10 kΩ

8.4.2 Continuous Waveform Generation (CWG) Mode

The DACx3701 implement a continuous waveform generation feature. To set the device to this mode, set the

START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous

waveform based on the FUNC_CONFIG bits (address D1h). Table 8-6 shows the continuous waveforms that can

be generated in this mode. The frequency of the waveform depends on the resistive and capacitive load on the

OUT pin, high and low codes, and slew rate settings as shown in the following equations.

SQUARE WAVE

2 SLEW _ RATE

(3)

TRIANGLE WAVE

MARGIN _ HIGH MARGIN _ LOW

2 SLEW _ RATE

CODE _ STEP

u ¨

(4)

SAWTOOTH WAVE

MARGIN _ HIGH MARGIN _ LOW

SLEW _ RATE

CODE _ STEP

u ¨

(5)

where:

• SLEW_RATE is the programmable DAC slew rate specified in Table 8-4.

• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.

• CODE_STEP is the programmable DAC step code in Table 8-3.

DAC53701, DAC43701

SLASEY5 – DECEMBER 2020

www.ti.com

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