DAC53701 datasheet(39/59 Pages) TI2

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8.6.4 TRIGGER Register (address = D3h) [reset = 0008h]

Figure 8-10. TRIGGER Register

DEVICE_UNLOCK_CODE

GPI_

DEVICE_

CONFIG_

RESET

START_

FUNC_

GEN

PMBUS_

MARGIN_

HIGH

PMBUS_

MARGIN_

LOW

NVM_

RELOAD

NVM_

PROG

SW_RESET

W-0h

X-0h R/W-0h

W-0h

R/W-0h

W-8h

Table 8-22. TRIGGER Register Field Descriptions

Bit

Field

Type

Reset

Description

15 - 12

DEVICE_UNLOCK_CODE

0000

Write 0101 to unlock the device to bypass DEVICE_LOCK bit.

Don't care

GPI_EN

R/W

0: GPI disabled

1: GPI enabled

DEVICE_CONFIG_RESET

0: Device configuration reset not initiated

1: Device configuration reset initiated. All registers loaded with

factory reset values.

START_FUNC_GEN

R/W

0: Continuous waveform generation mode disabled

1: Continuous waveform generation mode enabled, device

generates continuous waveform based on FUNC_CONFIG

(address D1h), MARGIN_LOW (address 26h), MARGIN_HIGH

(address 25h), and SLEW_RATE and CODE_STEP (address

D1h) bits.

PMBUS_MARGIN_HIGH

R/W

0: PMBus margin high command not initiated

1: PMBus margin high command initiated, DAC output margins

high to MARGIN_HIGH code (address 25h). This bit automatically

resets to 0 after the DAC code reaches MARGIN_HIGH value.

PMBUS_MARGIN_LOW

R/W

0: PMBus margin low command not initiated

1: PMBus margin low command initiated, DAC output margins

low to MARGIN_LOW code (address 26h). This bit automatically

resets to 0 after the DAC code reaches MARGIN_LOW value.

NVM_RELOAD

R/W

0: NVM reload not initiated

1: NVM reload initiated, applicable DAC registers loaded with

corresponding NVM. NVM_BUSY bit set to 1 which this operation

is in progress.. This bit is self-resetting.

NVM_PROG

R/W

0: NVM write not initiated

1: NVM write initiated, NVM corresponding to applicable DAC

registers loaded with existing register settings. NVM_BUSY bit

set to 1 which this operation is in progress. This bit is self-

resetting.

3 - 0

SW_RESET

1000

1000: Software reset not initiated

1010: Software reset initiated, DAC registers loaded with

corresponding NVMs, all other registers loaded with default

settings.

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DAC53701, DAC43701

SLASEY5 – DECEMBER 2020

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