DAC53701 datasheet(6/59 Pages) TI2

6 / 59 page

7.5 Electrical Characteristics (continued)

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,

DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive

load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VFB dc output impedance(3)

DAC output enabled, DAC reference tied to VDD (gain

= 1x) or internal reference (gain = 1.5x or 2x)

160

200

240

kΩ

DAC output enabled, internal VREF, gain = 3x or 4x

192

240

288

VOUT + VFB dc output

leakage(2)

At start up, measured when DAC output is disabled

and held at VDD / 2 for VDD = 5.5 V

Power supply rejection ratio

(dc)

Internal VREF, gain = 2x, DAC at midscale;

VDD = 5 V ±10%

0.25

mV/V

DYNAMIC PERFORMANCE

tsett

Output voltage settling time

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, VDD = 5.5 V

µs

1/4 to 3/4 scale and 3/4 to 1/4 scale settling to

10%FSR, VDD = 5.5 V, internal VREF, gain = 4x

Slew rate

VDD = 5.5 V

V/µs

Power-on glitch magnitude

At startup (DAC output disabled), RL = 5 kΩ,

CL = 200 pF

At startup (DAC output disabled), RL = 100 kΩ

200

Output enable glitch

magnitude

DAC output disabled to enabled (DAC registers at zero

scale, RL = 100 kΩ

250

Output noise voltage (peak to

peak)

0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V

µVPP

Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at

midscale, VDD = 5.5 V

Output noise density

Measured at 1 kHz, DAC at midscale, VDD = 5.5 V

0.2

µV/√Hz

Internal VREF, gain = 4x, measured at 1 kHz, DAC at

midscale, VDD = 5.5 V

0.7

Power supply rejection ratio

(ac)(3)

Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine

wave superimposed on power supply voltage, DAC at

midscale

–71

Code change glitch impulse

±1 LSB change around mid code (including

feedthrough)

nV-s

Code change glitch impulse

magnitude

±1 LSB change around mid code (including

feedthrough)

VOLTAGE REFERENCE

Initial accuracy

TA = 25°C

1.212

Reference output temperature

coefficient(2)

ppm/°C

EEPROM

Endurance(2)

–40°C ≤ TA ≤ +85°C

20000

Cycles

TA > 85°C

1000

Data retention(2)

TA = 25°C

Years

TA = 125°C

EEPROM programming write

cycle time(2)

DIGITAL INPUTS

Digital feedthrough

DAC output static at midscale, fast mode plus, SCL

toggling

nV-s

Pin capacitance

Per pin

DAC53701, DAC43701

SLASEY5 – DECEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: DAC53701 DAC43701

DAC53701 Datasheet(PDF) 6 Page - Texas Instruments

DAC53701 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL