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STA380WS Datasheet(PDF) 15 Page - STMicroelectronics |
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STA380WS Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 48 page  DocID024426 Rev 1 15/48 STA380WS Electrical specifications 3.6 Power-on/off sequences The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn- on and turn-off. Figure 3. Power-on sequence Figure 4. Power-off sequence Don’t care TR Don’t care Don’t care TC Don’t care TR Don’t care Don’t care TC TR = minimum time between XTI master clock stable and reset removal: 1 ms TC = minimum time between reset removal and I2C program sequence start: 1 ms No specific VCC and VDD_DIG turn-on sequence is required Clock stable means: fmax - fmin < 1 MHz VCC VDD_DIG XTI RESET PWRDN Bit EAPD Register 0x05 Don’t care Don’t care Don’t care FE Don’t care Don’t care Don’t care Don’t care Don’t care FE Don’t care Don’t care No specific VCC and VDD_DIG turn-off sequence is required VCC VDD_DIG XTI Mute Bit EAPD Register 0x05 Register 0x07 Obsolete Product(s) - Obsolete Product(s) |
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