SC16C852LIB datasheet(16/63 Pages) NXP

16 / 63 page

SC16C852L_3

Product data sheet

Rev. 03 — 18 January 2008

16 of 63

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

the receive FIFO passes the programmed trigger level. To clear this condition, the

SC16C852L will transmit the programmed Xon1/Xon2 characters as soon as the number

of characters in the receive FIFO drops below the programmed trigger level.

6.7 Special character detect

A special character detect feature is provided to detect an 8-bit character when EFR[5] is

set. When an 8-bit character is detected, it will be placed on the user-accessible data

stack along with normal incoming RX data. This condition is selected in conjunction with

EFR[3:0] (see Table 26). Note that software ﬂow control should be turned off when using

this special mode by setting EFR[3:0] to all zeroes.

The SC16C852L compares each incoming receive character with Xoff2 data. If a match

occurs, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate

detection of a special character. Although Table 10 “SC16C852L internal registers” shows

Xon1, Xon2, Xoff1, Xoff2 with eight bits of character information, the actual number of bits

is dependent on the programmed word length. Line Control Register bits LCR[1:0] deﬁne

the number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length

selected by LCR[1:0] also determines the number of bits that will be used for the special

character comparison. Bit 0 in Xon1, Xon2, Xoff1, Xoff2 corresponds with the LSB bit for

the received character.

6.8 Interrupt priority and time-out interrupts

The interrupts are enabled by IER[7:0]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC16C852L

will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to

continuing operations. The ISR indicates the current singular highest priority interrupt

only. A condition can exist where a higher priority interrupt masks the lower priority

interrupt(s) (see Table 15). Only after servicing the higher pending interrupt will the lower

priority interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

Receive Data Ready and Receive Time-Out have the same interrupt priority (when

enabled by IER[0]), and it is important to serve these interrupts correctly. The receiver

issues an interrupt after the number of characters have reached the programmed trigger

level. In this case, the SC16C852L FIFO may hold more characters than the programmed

trigger level. Following the removal of a data byte, the user should re-check LSR[0] to see

if there are any additional characters. A Receive Time-Out will not occur if the receive

FIFO is empty. The time-out counter is reset at the center of each stop bit received or

each time the Receive Holding Register (RHR) is read. The actual time-out value is

4 character time, including data information length, start bit, parity bit, and the size of stop

bit, that is, 1

×, 1.5×, or 2× bit times.

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