SC16C852LIB datasheet(10/63 Pages) NXP

10 / 63 page

SC16C852L_3

Product data sheet

Rev. 03 — 18 January 2008

10 of 63

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

RXA

Receive data A, B. These inputs are associated with individual

serial channel data to the SC16C852L receive input circuits, A

through B. The RX signal will be a logic 1 during reset, idle (no

data), or when not receiving data. During the local loopback mode,

the RXA/RXB input pin is disabled and TX data is connected to the

UART RX input, internally.

RXB

RXRDYA

--O

Receive Ready A, B (active LOW). This function provides the

RX FIFO/RHR status for individual receive channels (A to B).

RXRDY is primarily intended for monitoring DMA mode 1 transfers

for the receive data FIFOs. A logic 0 indicates there is a receive

data to read/upload, that is, receive ready status with one or more

RX characters available in the FIFO/RHR. This pin is a logic 1

when the FIFO/RHR is empty or when the programmed trigger

level has not been reached. This signal can also be used for single

mode transfers (DMA mode 0).

RXRDYB

TXA

Transmit data A, B. These outputs are associated with individual

serial transmit channel data from the SC16C852L. The TX signal

will be a logic 1 during reset, idle (no data), or when the transmitter

is disabled. During the local loopback mode, the TXA/TXB output

pin is disabled and TX data is internally connected to the UART RX

input.

TXB

TXRDYA

--O

Transmit Ready A, B (active LOW). These outputs provide the

TX FIFO/THR status for individual transmit channels (A to B).

TXRDY is primarily intended for monitoring DMA mode 1 transfers

for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, that is, at lease

one location is empty and available in the FIFO or THR. This pin

goes to a logic 1 (DMA mode 1) when there are no more empty

locations in the FIFO or THR. This signal can also be used for

single mode transfers (DMA mode 0).

TXRDYB

--O

VDD

Power supply input.

VSS

13[1]

Signal and power ground.

XTAL1

Crystal or external clock input. Functions as a crystal input or as

an external clock input. A crystal can be connected between this

pin and XTAL2 to form an internal oscillator circuit. Alternatively, an

external clock can be connected to this pin to provide custom data

rates (see Section 6.9 “Programmable baud rate generator”).

See Figure 8.

XTAL2

Output of the crystal oscillator or buffered clock. (See also

XTAL1.) Crystal oscillator output or buffered clock output. Should

be left open if an external clock is connected to XTAL1.

Table 2.

Pin description …continued

Symbol

Type

Description

LQFP48

HVQFN32

TFBGA36

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