SC16C852LIB datasheet(9/63 Pages) NXP

9 / 63 page

SC16C852L_3

Product data sheet

Rev. 03 — 18 January 2008

9 of 63

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

INTA/IRQ

When 16/68 pin is at logic 1 or unconnected, this output becomes

channel A interrupt output. The output state is deﬁned by the user

through the software setting of MCR[3]. INTA is set to the active

mode and OP2A output to a logic 0 when MCR[3] is set to a

logic 1. INTA is set to the 3-state mode and OP2A is set to a

logic 1 when MCR[3] is set to a logic 0.

When 16/68 pin is at logic 0, this output becomes device interrupt

output (active LOW, open-drain). An external pull-up resistor to

VDD is required.

INTB/n.c.

When 16/68 pin is at logic 1 or unconnected, this output becomes

channel B interrupt output. The output state is deﬁned by the user

through the software setting of MCR[3]. INTB is set to the active

mode and OP2B output to a logic 0 when MCR[3] is set to a

logic 1. INTB is set to the 3-state mode and OP2B is set to a

logic 1 when MCR[3] is set to a logic 0.

When 16/68 pin is at logic 0, this output is not used.

IOR/VDD

When 16/68 pin is at logic 1, this input becomes the read strobe

(active LOW). When 16/68 pin is at logic 0, this input pin is not

used and should be connected to VDD.

IOW/R/W

When 16/68 pin is at logic 1 or unconnected, this input becomes

the write strobe (active LOW).

When 16/68 pin is at logic 0, this input becomes read strobe when

it is at logic HIGH, and write strobe when it is at logic LOW.

OP2A

Output 2 (user-deﬁned). This function is associated with

individual channels, A through B. The state at these pin(s) are

deﬁned by the user and through MCR register bit 3. INTA, INTB

are set to the active mode and OP2 to logic 0 when MCR[3] is set

to a logic 1. INTA, INTB are set to the 3-state mode and OP2 to a

logic 1 when MCR[3] is set to a logic 0 (see Table 21 “Modem

Control Register bits description”, bit 3). Since these bits control

both the INTA, INTB operation and OP2 outputs, only one function

should be used at one time, INT or OP2.

OP2B

RESET/

RESET

Master Reset. When 16/68 pin is at logic 1 or unconnected, this

input becomes the RESET pin (active HIGH).

When 16/68 pin is at logic LOW, this input pin becomes RESET

(active LOW). (See Section 7.23 “SC16C852L external reset

condition and software reset” for initialization details.)

RIA

Ring Indicator (active LOW). These inputs are associated with

individual UART channels, A through B. A logic 0 on this pin

indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate an

interrupt if modem status interrupt is enabled.

RIB

RTSA

Request to Send (active LOW). These outputs are associated

with individual UART channels, A through B. A logic 0 on the RTSx

pin indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register MCR[1] will set this

pin to a logic 0, indicating data is available. After a reset this pin

will be set to a logic 1.

RTSB

Table 2.

Pin description …continued

Symbol

Type

Description

LQFP48

HVQFN32

TFBGA36

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