SC16C852LIB datasheet(61/63 Pages) NXP

61 / 63 page

SC16C852L_3

Product data sheet

Rev. 03 — 18 January 2008

61 of 63

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

14. Revision history

Table 44.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SC16C852L_3

20080118

Product data sheet

SC16C852L_2

Modiﬁcations:

• added TFBGA36 package option

• Table 10 “SC16C852L internal registers”, sub-section “Second special register set”:

– TXLVLCNT changed from “R/W” to “R”

– RXLVLCNT changed from “R/W” to “R”

• Section 7.12 “Transmit FIFO Level Count (TXLVLCNT)”, 2nd sentence: changed from “It reports the

number of characters available ...” to “It reports the number of spaces available ...”

• Table 38 “Static characteristics”:

– changed maximum IDD(sleep) from “80 µA” to “5 µA”

– changed maximum IDD(lp) from “80 µA” to “5 µA”

• Table 39 “Dynamic characteristics - Intel or 16 mode”:

– minimum tsu(A) changed from 5 ns to 0 ns

– maximum td(IOR-Q) changed from 20 ns to 40 ns

• Table 40 “Dynamic characteristics - Motorola or 68 mode”: maximum td(CS-Q) changed from 20 ns to

40 ns

SC16C852L_2

20070125

Product data sheet

SC16C852L_1

20061109

Objective data sheet

SC16C852LIB Datasheet(PDF) 61 Page - NXP Semiconductors