SC16C852LIB datasheet(14/63 Pages) NXP

14 / 63 page

SC16C852L_3

Product data sheet

Rev. 03 — 18 January 2008

14 of 63

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

6.4 FIFO operation

6.4.1 32-byte FIFO mode

When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the

‘First extra feature register set’ are empty (0x00) the transmit and receive trigger levels are

set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward

compatible to the SC16C652B (see Table 6), and the FIFO sizes are 32 entries. The

transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).

It should be noted that the user can set the transmit trigger levels by writing to the FCR,

but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section

includes a time-out function to ensure data is delivered to the external CPU (see

Section 6.8). Please refer to Table 13 and Table 14 for the setting of FCR[7:4].

6.4.2 128-byte FIFO mode

When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘ﬁrst extra feature

set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the

transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128

with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive

trigger levels can be set to any value between 1 and 128 with granularity of 1.

When the effective FIFO size changes (that is, when FCR[0] toggles or when the

combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between

equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will

be lost).

6.5 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C852L monitors the

CTSA/CTSB pin for a remote buffer overﬂow indication and controls the RTSA/RTSB pin

for local buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6]

(RTS) and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1

indicating a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]),

and the SC16C852L will suspend TX transmissions as soon as the stop bit of the

character in process is shifted out. Transmission is resumed after the CTSx input returns

to a logic 0, indicating more data may be sent.

When AFCR1[2] is set to logic 1 then the function of CTSA/CTSB pin is mapped to the

DSRA/DSRB pin, and the function of RTSA/RTSB is mapped to DTRA/DTRB pin. DSRx

and DTRx pins will behave as described above for CTS and RTS.

Table 6.

Interrupt trigger level and ﬂow control mechanism

FCR[7:6]

FCR[5:4]

INTA/INTB pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

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