PCM1795 datasheet(21/68 Pages) TI2

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(SCKH)

SystemClock

(SCK)

(SCKL)

0.8V

High

Low

(SCY)

PCM1795

www.ti.com

SLES248A – MAY 2009 – REVISED MARCH 2015

7.4 Device Functional Modes

•

SPI Mode is selected by connecting MSEL to DGND. SPI mode uses four signal lines and allows higher

speed full-duplex communication between the host and the PCM1795 device.

•

I2C Mode is selected by connecting MSEL to VDD. I

2C uses two signal lines for half-duplex communication,

and used in a variety of devices.

•

I2S input Mode is selected by default and is controlled by Register 20 bit 5.

•

DSD input Mode is selected by setting Register 20 bit 5 high.

•

TDMCA Mode is enabled when the PCM1795 device receives an LRCK signal with a pulse duration of two

BCK clocks.

7.5 Programming

7.5.1 System Clock and Reset Functions

7.5.1.1 System Clock Input

The PCM1795 requires a system clock to operate the digital interpolation filters and advanced segment DAC

modulators. The system clock is applied at the SCK input (pin 7). The PCM1795 has a system clock detection

circuit that automatically senses the frequency at which the system clock is operating. Table 3 shows examples

of system clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma (

ΔΣ)

modulator is selected as 128 fS, the system clock frequency is required to be greater than 256 fS.

Figure 39 and Table 4 show the timing requirements for the system clock input. For optimal performance, it is

important to use a clock source with low phase jitter and noise. The Texas Instruments PLL1700 family of

multiclock generators is an excellent choice to provide the PCM1795 system clock.

Table 3. System Clock Rates for Common Audio Sampling Frequencies

SYSTEM CLOCK FREQUENCY (fSCK) (MHz)

SAMPLING FREQUENCY

(kHz)

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

4.096(1)

6.144(1)

8.192

12.288

16.384

24.576

44.1

5.6488(1)

8.4672

11.2896

16.9344

22.5792

33.8688

6.144(1)

9.216

12.288

18.432

24.576

36.864

12.288

18.432

24.576

36.864

49.152(1)

73.728(1)

192

24.576

36.864

49.152(1)

73.728(1)

X(2)

(1)

This system clock rate is not supported in I2C fast mode.

(2)

This system clock rate is not supported for the given sampling frequency.

Figure 39. System Clock Input Timing

Table 4. System Clock Input Timing Characteristics for Figure 39

MIN

MAX

UNIT

t(SCY)

System clock pulse cycle time

t(SCKH)

System clock pulse duration, high

0.4t(SCY)

t(SCKL)

System clock pulse duration, low

0.4t(SCY)

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