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PCM1795 Datasheet(PDF) 9 Page - Texas Instruments

Part # PCM1795
Description  PCM1795 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog Converter
PDF  68 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

PCM1795 Datasheet(HTML) 9 Page - Texas Instruments

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SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
RepeatedStart
t
(RS-SU)
t
(RS-HD)
t
(SDA-F)
t
(SDA-R)
t
(P-SU)
Stop
t
(SP)
PCM1795
www.ti.com
SLES248A – MAY 2009 – REVISED MARCH 2015
6.6 Timing Requirements
MIN
MAX
UNIT
Standard
100
f(SCL)
SCL clock frequency
kHz
Fast
400
Standard
4.7
t(BUF)
Bus free time between stop and start conditions
μs
Fast
1.3
Standard
4.7
t(LOW)
Low period of the SCL clock
μs
Fast
1.3
Standard
4
μs
t(HI)
High period of the SCL clock
Fast
600
ns
Standard
4.7
μs
t(RS-SU)
Setup time for (repeated) start condition
Fast
600
ns
t(S-HD)
Standard
4
μs
Hold time for (repeated) start condition
t(RS-HD)
Fast
600
ns
Standard
250
t(D-SU)
Data setup time
ns
Fast
100
Standard
0
900
t(D-HD)
Data hold time
ns
Fast
0
900
Standard
20 + 0.1 CB
1000
t(SCL-R)
Rise time of SCL signal
ns
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
Rise time of SCL signal after a repeated start condition
t(SCL-R1)
ns
and after an acknowledge bit
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
t(SCL-F)
Fall time of SCL signal
ns
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
t(SDA-R)
Rise time of SDA signal
ns
Fast
20 + 0.1 CB
300
Standard
20 + 0.1 CB
1000
t(SDA-F)
Fall time of SDA signal
ns
Fast
20 + 0.1 CB
300
Standard
4
μs
t(P-SU)
Setup time for stop condition
Fast
600
ns
C(B)
Capacitive load for SDA and SCL line
400
pF
t(SP)
Pulse duration of suppressed spike
Fast
50
ns
VNH
Noise margin at high level for each connected device (including hysteresis)
0.2 VDD
V
Figure 1. Timing Definition on the I2C Bus
Copyright © 2009–2015, Texas Instruments Incorporated
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Product Folder Links: PCM1795



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