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PCM1795 Datasheet(PDF) 28 Page - Texas Instruments |
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PCM1795 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 68 page  PCM1795 SLES248A – MAY 2009 – REVISED MARCH 2015 www.ti.com Register Maps (continued) Table 9. User-Programmable Function Controls (continued) DF FUNCTION DEFAULT REGISTER BIT PCM DSD BYPASS Sampling rate selection for de-emphasis De-emphasis disabled Register 18 DMF[1:0] Yes Yes(1) No Disabled, 44.1 kHz, 48 kHz, 32 kHz De-emphasis control De-emphasis disabled Register 18 DME Yes No No Disabled, enabled Soft mute control Mute disabled Register 18 MUTE Yes No No Soft mute disabled, enabled Output phase reversal Normal Register 19 REV Yes Yes Yes Normal, reverse Attenuation speed selection ×1 fS Register 19 ATS[1:0] Yes No No ×1fS, ×(1/2)fS, ×(1/4)fS, ×(1/8)fS DAC operation control DAC operation enabled Register 19 OPE Yes Yes Yes Enabled, disabled Stereo DF bypass mode select Monaural Register 19 DFMS Yes No Yes Monaural, stereo Digital filter roll-off selection Sharp roll-off Register 19 FLT Yes No No Sharp roll-off, slow roll-off Infinite zero mute control Disabled Register 19 INZD Yes No Yes Disabled, enabled System reset control Normal operation Register 20 SRST Yes Yes Yes Reset operation, normal operation DSD interface mode control Disabled Register 20 DSD Yes Yes No DSD enabled, disabled Digital-filter bypass control DF enabled Register 20 DFTH Yes No Yes DF enabled, DF bypass Monaural mode selection Stereo Register 20 MONO Yes Yes Yes Stereo, monaural Channel selection for monaural mode data Left channel Register 20 CHSL Yes Yes Yes Left channel, Right channel ΔΣ oversampling rate selection ×64 fS Register 20 OS[1:0] Yes Yes(2) Yes ×64 fS, ×128 fS, ×32 fS PCM zero output enable Enabled Register 21 PCMZ Yes No Yes DSD zero output enable Disabled Register 21 DZ[1:0] Yes Yes No FUNCTION AVAILABLE ONLY FOR READ Zero detection flag Not zero = 0 ZFGL (for left channel) Register 22 Yes Yes Yes Not zero, zero detected Zero detected = 1 ZFGR (for right channel) Device ID (at TDMCA) — Register 23 ID[4:0] Yes No No (1) When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection. (2) When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operating rate selection. 7.6.1.2 Register Map The mode control register map is shown in Table 10. Registers 16 to 21 include an R/W bit that determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 10. Mode Control Register Map REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R/W 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Register 17 R/W 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Register 18 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE Register 19 R/W 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE RSV DFMS FLT INZD 28 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: PCM1795 |
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