L99DZ320 datasheet(54/146 Pages) STMICROELECTRONICS

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Figure 20. Watchdog in debug mode

OFF

long

open

window

Window

Mode

Debug

mode

Active mode

Enter

Debug mode

Exit from

Debug mode

Enter

Debug mode

Note:

Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence of 15

consecutive reset events is performed and the device enters the Forced_Vbat_Stby mode with the bit

FORCED_SLEEP_WD in SR8 set. If the device is woken up after such a forced VBAT_Standby condition and

the watchdog is still not serviced, the device, after one long open watchdog window reenters the same

Forced_Vbat_Stby mode until the next wake-up event. In this case, an additional watchdog failure is generated,

but the fail counter is not cleared, keeping the maximum number of 15 failures. This sequence is repeated until a

valid watchdog trigger event is performed by writing TRIG = 1.

3.6.1

Change watchdog timing

The watchdog trigger time can be configured by setting the WD_TIME (CR 17) bit. Writing to these bits is only

possible with the first SPI command after setting WD_CONFIG_EN = 1. The WD_CONFIG_EN bit is reset to 0

automatically with the next SPI command.

When FAIL_SAFE is active these SPI registers are not accessible and therefore in this case first the FAIL_SAFE

status needs to be cleared. In case of WD_FAIL, the clear is performed by trigging in long open window.

When a new configuration has been programmed, the watchdog continues behaving with the old configuration

until the next trig event.

The new value of WD_TIME is loaded in the watchdog module on the next trig event after the SPI configuration.

The following WD cycle uses the new programmed value.

3.7

Fail-safe mode

3.7.1

Temporary failures

L99DZ320 enters fail-safe mode in case of:

•

Watchdog failure

•

V1 failure (V1 < Vrth for t > tV1FS)

•

Thermal shutdown TSD2

The fail-safe functionality is also available in V1_Standby mode. During V1_Standby mode the fail-safe mode is

entered in the following cases:

•

V1 failure (V1 < Vrth for t > tV1FS)

•

Watchdog failure (if watchdog still running due to Iv1 > Icmp)

•

Thermal shutdown TSD2

In fail-safe mode the device returns to a fail-safe state. The fail-safe condition is indicated to the system in the

global status byte. The conditions during fail-safe mode are:

L99DZ320

Functional description

DS14235 - Rev 5

page 54/146

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