L99DZ320 datasheet(56/146 Pages) STMICROELECTRONICS

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In forced VBAT standby mode, all control registers are set to power on default.

The forced VBAT standby mode is entered in case of:

•

Multiple watchdog failures: FORCED_SLEEP_WD = 1 (15x watchdog failure)

•

Multiple thermal shutdown 2: FORCED_SLEEP_TSD2_V1SC = 1 (7x TSD2)

•

V1 short at turn on (V1 < V1fail for t > tV1short): FORCED_SLEEP_TSD2_V1SC (SR8) = 1

•

Loss of ground: SGNDLOSS (SR3) = 1

Table 53. Non recoverable failures conditions

Failure source

Failure condition

Diagnosis

Exit from

fail-safe mode

Microcontroller

(oscillator)

15 consecutive

watchdog failures

FS (global status byte) =1

WDFAIL (SR8) = 1

FORCED_SLEEP_WD (SR8) = 1

Wake-up

TRIG = 1 during long

open window

Read&Clear SR8

Short at turn on

FS (global status byte) = 1

V1FAIL = 1

FORCED_SLEEP_TSD2_V1SC (SR8) = 1

Wake-up

Read&Clear SR8

Temperature

7 times TSD2

FS (global status byte) =1

TW (SR7) = 1

TSD1 (SR8) = 1

TSD2 (SR8) = 1 FORCED_SLEEP_TSD2_V1SC (SR8) =

Wake-up

Read&Clear SR8

SGND

Loss of ground at

SGND pin

FS (global status byte) = 1

SGNDLOSS (SR3) = 1

Wake-up

Read&Clear SR3

3.8

Reset output

If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output “NRESET” is pulled up by the

internal pull-up resistor to V1 voltage after a reset delay time (tRD). This is necessary for a defined start of the

microcontroller when the application is switched on. Since the NRESET output is realized as an open drain

output, it is also possible to connect an external NRESET open drain NRESET source to the output. As soon as

the NRESET is released, the watchdog timing starts with a long open window.

Figure 21. NRESET pin

Data in

110 kΩ

Data out

A reset pulse is generated in case of:

•

V1 drops below Vrth (configurable by SPI) for t > tuv1

•

Watchdog failure

L99DZ320

Functional description

DS14235 - Rev 5

page 56/146

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