L99DZ320 datasheet(80/146 Pages) STMICROELECTRONICS

80 / 146 page

4.1.1

Physical layer

Figure 40. SPI pin description

CSN

SCK

SDI

SDO

L99DZ320

µC

SPI Master

4.2

Signal description

•

Chip select not (CSN)

The communication interface is deselected, when this input signal is logically high. A falling edge on CSN enables

and starts the communication while a rising edge finishes the communication and the sent command is executed

when a valid frame is sent. During communication start and stop the serial clock (SCK) has to be logically low.

The serial data out (SDO) is in high impedance when CSN is high or a communication timeout was detected.

•

Serial clock (SCK)

This SCK provides the clock of the SPI. Data present at serial data input (SDI) is latched on the rising edge of

serial clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are

shifted out to serial data out (SDO).

•

Serial data input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge of serial clock (SCK).

•

Serial data output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial

clock (SCK).

4.2.1

Clock and data characteristics

The ST SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:

Figure 41. SPI signal description

CSN

SCK

SDI

SDO

LSB

MSB

LSB

The communication frame starts with the falling edge of the CSN (communication start). SCK has to be low.

The SDI data is then latched at all the following rising SCK edges into the internal shift registers.

After communication start the SDO leaves 3-state mode and presents the MSB of the data shifted out to SDO. At

all the following falling SCK edges data is shifted out through the internal shift registers to SDO.

L99DZ320

Serial peripheral interface (SPI)

DS14235 - Rev 5

page 80/146

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