L99DZ320 datasheet(99/146 Pages) STMICROELECTRONICS

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6.4

Control registers

6.4.1

Control register 1 (CR1, 0x26)

Table 76. Control register 1

Bit

name

Reset

value

Access

Table 77. CR1 signals description

Bit

Name

Description

CAN_LOOP_EN

CAN looping of TXDC to RXDC

0: CAN looping disabled (default)

1: CAN looping enabled

LIN_TXD_TOUT

LIN TXD timeout detection

0: LIN TXD timeout detection disabled

1: LIN TXD timeout detection enabled (default)

LIN_WU_CONFIG

Configuration of LIN wake-up behavior

0: wake-up at recessive-dominant-recessive with t_dom > 28 μs (default) (according to LIN 2.2a and

hardware requirements for transceivers version 1.3)

1: wake-up at recessive-dominant transition

20-19

RESERVED

DISABLE_CP_DITH

Charge pump dithering

0: charge pump dithering enabled (default)

1: charge pump dithering disabled

ICMP_CONFIG_EN

ICMP configuration enable

0: writing ICMP = 1 is blocked (writing ICMP = 0 is possible); (default)

1: writing ICMP = 1 is possible with next SPI command

bit is automatically reset to 0 after next SPI command

WD_CONFIG_EN

Watchdog configuration enable

0: writing to WD configuration (CR17 [0:1]) is blocked (default)

1: writing to WD configuration bits is possible with next SPI command

bit is automatically reset to 0 after next SPI command

15-14

RESERVED

MASK_TW

0: thermal warning is not masked (default)

1: thermal warning is masked that is reported as a global warning (GSB bit 25) but not as a global error (GSB

bit 31)

RESERVED

MASK_OL

0: open-load condition at all outputs are not masked (default)

1: open-load condition at all outputs are masked, that is reported as a functional error (GSB bit 27), but not as

a global error (GSB bit 31)

L99DZ320

SPI Registers

DS14235 - Rev 5

page 99/146

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