L99DZ320 datasheet(62/146 Pages) STMICROELECTRONICS

62 / 146 page

•

Serial data in (DI)

The input pin is used to transfer serial data into the device. The data applied to the DI is sampled at the

rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN

signal the content of the shift register is transferred to the data input register. The writing to the selected

data input register is only enabled if exactly 32 bits are transmitted within one communication frame (that is

CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This

safety function is implemented to avoid an activation of the output stages by a wrong communication

frame.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI

bus by controlling the CSN signal of the connected IC's is recommended.

•

Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and switches from high

impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of

the CLK input after a high to low transition of the CSN pin transfers the content of the selected status

•

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is

sampled at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK

signal. The SPI can be driven with a CLK frequency up to 4 MHz.

3.12

Power supply fail

3.12.1

VS supply failure

VS overvoltage

If the supply voltage VS reaches the overvoltage threshold VSOV:

•

LIN remains enabled

•

CAN remains enabled

•

HB4, ..., HB6 and HS7, .. , HS14 are turned off (default)

•

The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN = 0)

•

Charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal

operating voltage)

•

H-bridge gate driver is switched into sink condition

•

Recovery of outputs after overvoltage condition is configurable by SPI

–

VS_LOCK_EN (CR16) = 1: outputs are off until Read&Clear VS_OV (SR7)

–

VS_LOCK_EN (CR16) = 0: outputs turned on automatically after VS overvoltage condition has

recovered

•

The overvoltage bit VS_OV (SR7) is set and can be cleared with a ‘Read&Clear’ command. The

overvoltage bit is reset automatically if VS_ LOCK_EN (CR16) = 0 and the overvoltage condition has

recovered

VS undervoltage

If the supply voltage Vs drops below the undervoltage threshold voltage (VSUV):

•

LIN remains enabled

•

CAN remains enabled

•

HB4, ..., HB6 and HS7, .. , HS14 are turned OFF (default). The shutdown of outputs may be disabled by

SPI (VS_UV_SD_EN (CR16) = 0).(1)

•

Recovery of outputs after undervoltage condition is configurable by SPI:

–

VS_LOCK_EN (CR16) = 1: outputs are off until Read&Clear VS_UV (SR7)

–

VS_LOCK_EN (CR16) = 0: outputs turned on automatically after VS undervoltage condition has

recovered

•

The undervoltage bit (VSUV) is set and can be cleared with a ‘Read and Clear’ command. The undervoltage

bit is removed automatically if VS_LOCK_EN = 0 and the undervoltage condition has recovered

•

H-bridge gate driver passes to resistive low condition. (If VS_UV_SD EN = 1, otherwise remains

unchanged until CP_LOW = 1)

L99DZ320

Functional description

DS14235 - Rev 5

page 62/146

L99DZ320 Datasheet(PDF) 62 Page - STMicroelectronics

L99DZ320 Datasheet(HTML) 62 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL