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RFM95/96/97/98(W)

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5. RFM95/96/97/98(W) Analog & RF Frontend Electronics

5.1. Power Supply Strategy

The RFM95/96/97/98(W) employs an internal voltage regulation scheme which provides stable operating voltage, and

hence device characteristics, over the full industrial temperature and operating voltage range of operation. This includes

up to

+17 dBm of RF output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.

The RFM95/96/97/98(W) can be powered from any low-noise voltage source via pins VBAT_ANA, VBAT_RF and

VBAT_DIG. Decoupling capacitors should be connected, as suggested in the reference design of the applications section

of this document, on VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators.

5.2. Low Battery Detector

A low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage

dropping below a programmable threshold that is adjustable through the register RegLowBat. The interrupt signal can be

mapped to any of the DIO pins by programming RegDioMapping.

5.3. Frequency Synthesis

5.3.1. Crystal Oscillator

The crystal oscillator is the main timing reference of the RFM95/96/97/98(W). It is used as the reference for the PLL’s

frequency synthesis and as the clock signal for all digital processing.

The crystal oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal reference used, for

more information on the electrical specification of the crystal see Section 2.3. The crystal connects to the Pierce oscillator

on pins XTA and XTB. The RFM95/96/97/98(W) optimizes the startup time and automatically triggers the PLL when the

oscillator signal is stable.

RFM95 Datasheet(PDF) 76 Page - Shenzhen Hope Microelectronics Co., Ltd.