ADPL12002/ADPL12003

20V, 2.5A/3.5A, Fully Integrated Synchronous

Buck Converter

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Analog Devices | 9

Pin Configurations

14

5

1

15

4

6

NC

ADPL12002

ADPL12003

EN

SUP

BST

NC

SUP

10

13

12

11

2

3

9

8

7

15 FC2QFN

(3.0mm x 3.0mm)

Pin Descriptions

PIN

NAME

FUNCTION

1

EN

High-Voltage-Tolerant, Active-High Digital Enable Input. Drive EN high to enable the buck converter.

2, 8

NC

Not Connected.

3, 7

SUP

Internal High-Side Supply Input. SUP provides power to the internal switch and LDO. Bypass SUP to

PGND with 0.1μF and 2.2μF ceramic capacitors. Place the 0.1μF capacitor as close to the SUP and PGND

pins as possible, followed by the 2.2μF capacitor.

4, 6

PGND

Power Ground.

5

LX

Inductor Connection. Connect LX to the switched side of the inductor.

9

BST

Boost Flying Capacitor Connection for High-Side FET Gate Voltage. Connect a 0.1μF ceramic capacitor

between BST and LX.

10

GND

Quiet Analog Ground.

11

BIAS

1.8V Internal BIAS Supply. Connect a minimum of 2.2μF ceramic capacitor from BIAS to PGND.

12

SPS

Spread-Spectrum Enable. Connect to logic high to enable the spread spectrum of the internal oscillator or

logic low to disable the spread spectrum.

13

FB

Feedback Input. It acts as an output voltage feedback input. Connect an external resistor-divider between

the buck output, FB, and GND to set the output voltage.

14

PGOOD

Open-Drain Power-Good Output. Connect PGOOD to BIAS or an external positive power supply with a

pullup resistor.

15

SYNC

External Clock Synchronization Input. Connect an external clock in the given frequency range to enable

external clock synchronization. Connect SYNC to low to enable skip mode. Connect SYNC to high to

enable FPWM mode.