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TUSB2046B, TUSB2046I

SLLS413L – FEBRUARY 2000 – REVISED JUNE 2017

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Product Folder Links: TUSB2046B TUSB2046I

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Copyright © 2000–2017, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

11.1.1 Placement

1. A 0.1-μF should be placed as close as possible on VCC power pin.

2. The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB

connector.

3. If a crystal is used, it must be placed as close as possible to the TUSB2046x’s XTAL1 and XTAL2 pins.

4. Place voltage regulators as far away as possible from the TUSB2046x, the crystal, and the differential pairs.

5. In general, the large bulk capacitors associated with the power rail should be placed as close as possible to

the voltage regulators.

11.1.2 Differential Pairs

1. Must be designed with a differential impedance of 90Ω ±10%.

2. Route all differential pairs on the same layer adjacent to a solid ground plane.

3. Do not route differential pairs over any plane split.

4. Adding test points will cause impedance discontinuity and will therefore negative impact signal performance.

If test points are used, they should be placed in series and symmetrically. They must not be placed in a

manner that causes stub on the differential pair.

5. Avoid 90-degree turns in trace. The use of bends in differential traces should be kept to a minimum. When

bends are used, the number of left and right bends should be as equal as possible and the angle of the bend

should be

≥ 135 degrees. This will minimize any length mismatch causes by the bends and therefore

minimize the impact bends have on EMI.

6. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for USB

2.0 differential pair signals is 8 inches. Longer trace lengths require very careful routing to assure proper

signal integrity.

7. Match the etch lengths of the differential pair traces. The USB 2.0 differential pairs should not exceed 50 mils

relative trace length difference.

8. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. Any vias used should be placed as

close as possible to the TUSB2046x device.

9. Do not place power fuses across the differential pair traces.

11.1.3 Ground

TI recommends using only one board ground plane in the design. This provides the best image plane for signal

traces running above the plane. The thermal pad of the TUSB2046x and any of the voltage regulators should be

connected to this plane with vias. An earth or chassis ground is implemented only near the USB port connectors

on a different plane for EMI and ESD purposes.