XTAL1

C1

C2

C

L

XTAL2

11

TUSB2046B, TUSB2046I

www.ti.com

SLLS413L – FEBRUARY 2000 – REVISED JUNE 2017

Product Folder Links: TUSB2046B TUSB2046I

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Copyright © 2000–2017, Texas Instruments Incorporated

Feature Description (continued)

Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2046x supports four modes of

power management: bus-powered hub with either individual-port power-management or ganged-port power

management, and the self-powered hub with either individual-port power management or ganged-port power

management. TI supplies the complete hub solution with the TUSB2036 (2/3-port), TUSB2046x, and the

TUSB2077 (7-port) hubs along with the power-management devices needed to implement a fully USB

specification-compliant system.

8.3.2 Clock Generation

The input clock configuration logic of TUSB2046x is enhanced to accept a 6-MHz crystal or 48-MHz on-the-board

clock source with a simple tie-off change on TSTMODE (pin 31).

•

A 6-MHz input clock configuration is shown in Figure 5.

In this mode, both TSTMODE and TSTPLL/48MCLK pins must be tied to ground. The hub is configured to

use the 6-MHz clock on pins 30 and 29, which are XTAL1 and XTAL2, respectively, on the TUSB2046x. This

is identical to the TUSB2046.

Figure 5. 6-MHz Input Clock Configuration

NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd

are determined using a crystal from Fox Electronics – part number HC49U-6.00MHz 30\50\0-70\20, which means

±30 ppm at 25°C and ±50 ppm from 0°C to 70°C. The characteristics for the crystal include a load capacitance (CL) of

20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 Ω. In order to insure enough negative

resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 kΩ is recommended.

Figure 6. Crystal Tuning Circuit

•

A 48-MHz input clock configuration is shown in Figure 7.

In this mode, both TSTMODE and XTAL1 pins must be tied to 3.3-V VCC. The hub accepts the 48-MHz clock

input on TSTPLL/48MCLK (terminal 27). XTAL2 must be left floating (open) for this configuration. Only the

oscillator or the onboard clock source is accepted for this mode. A crystal cannot be used for this mode,

because the internal oscillator cell of the chip only supports the fundamental frequency.