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TDA2SA Datasheet(PDF) 286 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 286 Page - Texas Instruments |
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286 / 427 page  286 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF SPRS951F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated Table 7-64. USB3 and USB4 IOSETs (continued) SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX usb4_ulpi_d4 V4 6 usb4_ulpi_d5 V3 6 usb4_ulpi_d6 Y2 6 usb4_ulpi_d7 W2 6 usb4_ulpi_stp V9 6 usb4_ulpi_clk W9 6 usb4_ulpi_dir V7 6 usb4_ulpi_nxt U7 6 7.18 Serial Advanced Technology Attachment (SATA) The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate: • Gen2i, Gen2m, Gen2x: 3Gbps. • Gen1i, Gen1m, Gen1x: 1.5Gbps. NOTE For more information, see the SATA Controller section of the Device TRM. 7.19 Peripheral Component Interconnect Express (PCIe) The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane) (Single Lane and Flexible dual lane configuration). The device PCIe supports the following features: • 16-bit operation @250 MHz on PIPE interface (per 16-bit lane) • Supports 1 ports x 1 lane configuration • Single virtual channel (VC0), single traffic class (TC0) • Single function in end-point mode • Automatic width and speed negotiation • Max payload: 128 byte outbound, 256 byte inbound • Automatic credit management • ECRC generation and checking • Configurable BAR filtering • Legacy interrupt reception (RC) and generation (EP) • MSI generation and reception • PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions) • All PCI Device Power Management D-states with the exception of D3cold / L2 state The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and the PCI Local Bus Specification, revision 3.0. NOTE For more information, see the PCIe Controller section of the Device TRM. 7.20 Controller Area Network Interface (DCAN) |
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