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TDA2SA Datasheet(PDF) 287 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 287 Page - Texas Instruments |
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287 / 427 page  287 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Timing Requirements and Switching Characteristics Copyright © 2015–2019, Texas Instruments Incorporated The device provides two DCAN interfaces for supporting distributed realtime control with a high level of security. The DCAN interfaces implement the following features: • Supports CAN protocol version 2.0 part A, B • Bit rates up to 1 MBit/s • 64 message objects • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Software module reset • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Direct access to Message RAM during test mode • CAN Rx/Tx pins are configurable as general-purpose IO pins • Two interrupt lines (plus additional parity-error interrupts line) • RAM initialization • DMA support NOTE For more information, see the DCAN section of the Device TRM. NOTE The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx. NOTE Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter tolerance calculations must be performed to validate the implementation. Table 7-65 and Table 7-66 present timing and switching characteristics for DCANx Interface. Table 7-65. Timing Requirements for DCANx Receive NO. PARAMETER DESCRIPTION MIN NOM MAX UNIT - f(baud) Maximum programmable baud rate 1 Mbps - td(DCANRX) Delay time, DCANx_RX pin to receive shift register 15 ns Table 7-66. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit NO. PARAMETER DESCRIPTION MIN MAX UNIT - f(baud) Maximum programmable baud rate 1 Mbps - td(DCANTX) Delay time, Transmit shift register to DCANx_TX pin(1) 15 ns (1) These values do not include rise/fall times of the output buffer. 7.21 Ethernet Interface (GMAC_SW) The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII) in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY) management. |
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