TDA2SA datasheet(288/427 Pages) TI2

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mii _rxclk

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TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Timing Requirements and Switching Characteristics

NOTE

For more information, see the Ethernet Subsystem section of the Device TRM.

NOTE

The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as

MIIn, RMIIn and RGMIIn

CAUTION

The IO timings provided in this section are only valid if signals within a single

IOSET are used. The IOSETs are defined in the Table 7-71, Table 7-74,

Table 7-79 and Table 7-86.

CAUTION

The IO Timings provided in this section are only valid for some GMAC usage

modes when the corresponding Virtual IO Timings or Manual IO Timings are

configured as described in the tables found in this section.

Table 7-67 and Figure 7-45 present timing requirements for MIIn in receive operation.

7.21.1 GMAC MII Timings

Table 7-67. Timing Requirements for miin_rxclk - MII Operation

NO.

PARAMETER

DESCRIPTION

SPEED

MIN

MAX

UNIT

tc(RX_CLK)

Cycle time, miin_rxclk

10 Mbps

400

100 Mbps

tw(RX_CLKH)

Pulse duration, miin_rxclk high

10 Mbps

140

260

100 Mbps

tw(RX_CLKL)

Pulse duration, miin_rxclk low

10 Mbps

140

260

100 Mbps

tt(RX_CLK)

Transition time, miin_rxclk

10 Mbps

100 Mbps

Figure 7-45. Clock Timing (GMAC Receive) - MIIn operation

Table 7-68 and Figure 7-46 present timing requirements for MIIn in transmit operation.

TDA2SA Datasheet(PDF) 288 Page - Texas Instruments

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