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TDA2SA Datasheet(PDF) 296 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 296 Page - Texas Instruments

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rgmii _txc
n
(A)
rgmii _txd
n
[3:0]
(B)
rgmii _txctl
n
(B)
5
1st Half-byte
TXERR
TXEN
2nd Half-byte
4
4
2
3
1
6
[internal delay enabled]
296
TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
www.ti.com
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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Timing Requirements and Switching Characteristics
Copyright © 2015–2019, Texas Instruments Incorporated
Table 7-85. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
5
tosu(TXD-TXC)
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
(2)
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
6
toh(TXC-TXD)
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
(2)
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 1000Mbps operation requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched
within 50pS of rgmii0_txc.
(3) RGMII1 1000Mbps operation requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched
within 50pS of rgmii1_txc.
A.
TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B.
Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-53. GMAC Transmit Interface Timing RGMIIn operation
In Table 7-86 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
Table 7-86. GMAC RGMII IOSETs
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
GMAC RGMII1
rgmii1_txd3
C3
3
rgmii1_txd2
C4
3
rgmii1_txd1
B2
3
rgmii1_txd0
D6
3
rgmii1_rxd3
B3
3
rgmii1_rxd2
B4
3
rgmii1_rxd1
B5
3



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