TDA2SA datasheet(361/427 Pages) TI2

361 / 427 page

Signal 1

Power Plane

GND Plane

Signal 2

361

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

www.ti.com

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Consider the recommendations listed below to achieve proper ESD/EMI performance:

•

Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.

•

Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.

•

If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the

immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.

8.5.2.2.2.2 Analog, Digital, and PLL Partitioning

If separate power planes are used, they must be tied together at one point through a low-impedance

bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail

close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-

impedance circuit board ground plane.

8.5.2.2.2.3 Board Stackup

Because of the high frequencies associated with the USB, a printed circuit board with at least four layers

is recommended; two signal layers separated by a ground and power layer as shown in Figure 8-31.

Figure 8-31. Four-Layer Board Stack-Up

The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this

layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in

the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must

be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

8.5.2.2.2.4 Cable Connector Socket

Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists

immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground

before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors

coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop

out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note

that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their

respective planes as soon as possible, respecting the filtering that may be in place between the connector

pin and the plane. See Figure 8-32 for a schematic example.

Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting

onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10

Ω

and 50

Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the

cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,

VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be

valued between 47

Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to

approximately 1 GHz, as shown in Figure 8-32.

TDA2SA Datasheet(PDF) 361 Page - Texas Instruments

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