TDA2SA datasheet(358/427 Pages) TI2

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qspi1_sclk

qspi1_rtclk

QSPI device

clock input

QSPI device

IOx, CS#

qspi1_d[x], qspi1_cs[y]

10 Ω

Locate both R2 resistors

close together near the QSPI device

SPRS906_PCB_QSPI_01

358

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

•

Propagation delays and matching:

–

A to C = C to D = E to F.

–

Matching skew: < 60pS

–

A to B < 450pS

–

B to C = as small as possible (<60pS)

Figure 8-29. QSPI Interface High Level Schematic

(1) 0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-tuning if needed.

8.5

Differential Interfaces

8.5.1

General Routing Guidelines

To maximize signal integrity, proper routing techniques for differential signals are important for high-speed

designs. The following general routing guidelines describe the routing guidelines for differential lanes and

differential signals.

•

As much as possible, no other high-frequency signals must be routed in close proximity to the

differential pair.

•

Must be routed as differential traces on the same layer. The trace width and spacing must be chosen

to yield the differential impedance value recommended.

•

Minimize external components on differential lanes (like external ESD, probe points).

•

Through-hole pins are not recommended.

•

Differential lanes mustn’t cross image planes (ground planes).

•

No sharp bend on differential lanes.

•

Number of vias on the differential pairs must be minimized, and identical on each line of the differential

pair. In case of multiple differential lanes in the same interface, all lines should have the same number

of vias.

TDA2SA Datasheet(PDF) 358 Page - Texas Instruments

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