TDA2SA datasheet(134/427 Pages) TI2

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134

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Terminal Configuration and Functions

Table 4-29. Power Supply Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

cap_vbbldo_dspeve(1)

External capacitor connection for the DSP-EVE vbb ldo output

CAP

cap_vddram_mpu1(1)

External capacitor connection for the MPU SRAM array ldo1 output

CAP

K16

cap_vddram_mpu2(1)

External capacitor connection for the MPU SRAM array ldo2 output

CAP

K19

cap_vddram_core1(1)

External capacitor connection for the Core SRAM array ldo1 output

CAP

cap_vddram_core4(1)

External capacitor connection for the Core SRAM array ldo4 output

CAP

P19

cap_vbbldo_iva(1)

External capacitor connection for the IVA vbb ldo output

CAP

R20

cap_vddram_iva(1)

External capacitor connection for the IVA SRAM array ldo output

CAP

T20

cap_vddram_gpu(1)

External capacitor connection for the GPU SRAM array ldo output

CAP

Y13

cap_vbbldo_gpu(1)

External capacitor connection for the GPU vbb ldo output

CAP

Y14

cap_vddram_core3(1)

External capacitor connection for the Core SRAM array ldo3 output

CAP

Y15

cap_vddram_core5(1)

External capacitor connection for the Core SRAM array ldo5 output

CAP

Y16

(1) This pin must always must always be connected via a 1-uF capacitor to vss.

4.4.21 Test Interfaces

CAUTION

The I/O timings provided in Section 7 Timing Requirements and Switching

Characteristics are valid only if signals within a single IOSET are used. The

IOSETs are defined in the Table 7-139.

NOTE

For more information, see the On-Chip Debug Support / Debug Ports section of the device

TRM.

Table 4-30. Debug Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

tms

JTAG test port mode select. An external pullup resistor should be used on

this ball.

F18

tdi

JTAG test data

D23

tdo

JTAG test port data

F19

tclk

JTAG test clock

E20

trstn

JTAG test reset

D20

rtck

JTAG return clock

E18

emu0(1)

Emulator pin 0

G21

emu1(1)

Emulator pin 1

D24

emu2

Emulator pin 2

F10

emu3

Emulator pin 3

emu4

Emulator pin 4

emu5

Emulator pin 5

E1/ G11

emu6

Emulator pin 6

G2/ E9

emu7

Emulator pin 7

H7/ F9

emu8

Emulator pin 8

G1/ F8

emu9

Emulator pin 9

G6/ E7

emu10

Emulator pin 10

F2/ D8

emu11

Emulator pin 11

F3/ A5

emu12

Emulator pin 12

D1/ C6

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