REF pin. The second feedback path is through the feedback capacitor, CF = 2200pF, connected to the output of

the op amp. The circuit provides a loop gain phase margin of 86°. The noninverting input of the OPA387 buffer

has a low-pass filter with R = 1kΩ, C = 10nF to reduce the resistive divider thermal noise. Using any other load

capacitance requires recalculation of the stability components: RF, CF, and RISO. If modifying the REF bypass

capacitance, verify the circuit is stable with simulation using the OPA387 TINA-TI model (or PSpice®-for-TI

model). Confirm the circuit provides more than 60° of phase margin.

The results are shown in Table 8-2, which includes the typical signal-to-noise ratio (SNR) and total harmonic

distortion (THD) measurements. A 1kHz differential signal is applied and the signal amplitude is adjusted to

produce PGA848 output at -0.5dBFS of the ADC.

Table 8-2. PGA848 and ADS8860 FFT Data Summary, fSAMPLE = 1 MSPS, fIN = 1kHz, BW = 160kHz

PGA GAIN (V/V)

INPUT AMPLITUDE (VPP)

SNR (dB)

THD (dB)

ENOB (Bits)

0.5

9.79

91.84

-95.34

14.70

1

4.886

91.72

-95.45

14.69

2

2.443

91.35

-95.33

14.64

5

977.5m

88.57

-95.32

14.28

10

488.5m

84.00

-95.18

13.61

20

244.1m

78.98

-95.10

12.81

50

97.8m

72.36

-94.75

11.72

100

48.85m

67.16

-92.75

10.86

Performance and SNR are function of the system bandwidth. Setting the system bandwidth to fit application

requirements enables higher performance. In the previous example, reducing the PGA bandwidth to 23kHz by

setting CFB = 1nF improves the SNR at higher gains by almost 12dB as shown in Table 8-3.

Table 8-3. PGA848 and ADS8860 FFT Data Summary, fSAMPLE = 1 MSPS, fIN = 1kHz, BW = 23kHz

PGA GAIN (V/V)

INPUT AMPLITUDE (VPP)

SNR (dB)

THD (dB)

ENOB (Bits)

0.5

9.79

92.69

-93.90

14.69

1

4.886

92.70

-93.64

14.68

2

2.443

92.59

-93.28

14.64

5

977.5m

92.36

-93.25

14.62

10

488.5m

91.66

-93.17

14.55

20

244.1m

89.75

-93.27

14.35

50

97.8m

84.16

-93.15

13.60

100

48.85m

78.80

-92.64

12.77

8.3 Power Supply Recommendations

The nominal performance of the PGA848 is specified with input-stage supply and output-stage supply voltages

of ±15V, and VICM and VREF at mid-supply. Within the specified limits, custom input common-mode and output

common-mode voltages are usable without compromising performance; see also Section 6.3. To prevent

damage to internal circuitry, the output-stage power supplies are clamped to stay within the input-stage supply

voltage levels; see also Section 7.2.

CAUTION

Supply voltages higher than 40V (±20V) permanently damage the device. Parameters that vary over

supply voltage or temperature are shown in Typical characteristics section of this document.

www.ti.com

PGA848

SBOSAN4A – AUGUST 2025 – REVISED DECEMBER 2025

Copyright © 2025 Texas Instruments Incorporated

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