detrimental to a decompensated amplifier stability because this amplifier isolates the APD capacitance from the

noise gain transfer function. Equation 4 calculates the noise gain. The added PCB trace inductance between

the feedback network increases the denominator in Equation 4, thereby reducing the noise gain and the phase

margin. In cases where a leaded APD in a TO can is used, further minimize inductance by cutting the leads of

the TO can as short as possible. Also, consider edge mounting the photodiode on the PCB versus through the

hole, if the application allows.

To improve the layout in Figure 8-10, follow some of the guidelines in Figure 8-11. The two key rules to follow

are:

• Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value

of RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace

inductance and the amplifiers internal capacitance.

• Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible.

This configuration provides a more balanced layout and reduces the inductive isolation between the APD and

the feedback network.

Noise Gain = 1 + ZFZIN

(4)

where,

• ZF is the total impedance of the feedback network

• ZIN is the total impedance of the input network

CF

APD

Package

Trace inductance isolates

APD capacitance from the

amplifier noise gain

RF

1

PD

8 VS+

2

FB

7 OUT

3

IN±

6 NC

4

IN+

5 VS±

Thermal

Pad

VBIAS

Figure 8-10. Non-Ideal TIA Layout

VBIAS

Place RISO close to IN±

Close the loop close

to APD pins

1

PD

8 VS+

2

FB

7 OUT

3

IN±

6 NC

4

IN+

5 VS±

Thermal

Pad

APD

Package

CF

RF

RISO

Figure 8-11. Improved TIA Layout

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OPA818

SBOS940B – MAY 2019 – REVISED DECEMBER 2025

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