TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
TIMER / COUNTER
Preliminary
6-6
Watchdog Timer Configuration Register (TWDCFG)
0x80000270
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
TCKSEL
IEN
0
ISEL
EN
Watchdog timer is used for the system not to be stuck by generating a reset pulse or
interrupt automatically when the watchdog timer counter overflows to zero.
The programmer must clear the watchdog counter before it overflows by writing any
value to TWDCLR register. The duration can be chosen by selecting TCKSEL field
appropriately.
TCKSEL
[6:4]
TCK Select
k = 0 ~ 3
Undefined. Should not be used.
k = 4
TCK is internally generated from divider circuit. It is driven by TCLK, and
this value determines the division factor of this circuit. Division factor is 25.
k = 5, 6
TCK is internally generated from divider circuit. It is driven by TCLK, and
this value determines the division factor of this circuit. Division factor is 22k
k = 7
Undefined. Should not be used.
IEN [3]
Interrupt Enable
1
Watchdog Timer Interrupt is enabled.
This field is valid only if RST field is set to 0.
ISEL [1]
Interrupt Select
0
Watchdog timer generates the reset signal when it reaches to the
reference value, the reset signal is applied to every component in the
chip.
1
Watchdog timer does not generate reset signal although it reaches to the
reference value, and it continue counting from 0.
EN [0]
Watchdog Timer Enable
1
Watchdog timer is enabled. If the watchdog timer is disabled, its
counter goes to 0xE0, so when it is first enabled, user must clear the
counter by writing to TWDCLR register.
Watchdog Timer Clear Register (TWDCLR)
0x80000274
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
any value
The watchdog timer counter can be cleared to 0 by writing any value to this register.
If it is not cleared before it overflows, the watchdog timer generate reset signal to the
entire component of chip.
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