MAX9879 datasheet(28/32 Pages) AD

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MAX9879

Stereo Class D Audio Subsystem

with DirectDrive Headphone Amplifier

Maxim Integrated

actual speaker lead length. Select a capacitor less than

1nF based on EMI performance.

Input Capacitor

An input capacitor, CIN, in conjunction with the input

impedance of the MAX9879 forms a highpass filter that

removes the DC bias from an incoming signal. The AC-

coupling capacitor allows the amplifier to automatically

bias the signal to an optimum DC level. Assuming zero

source impedance, the -3dB point of the highpass filter

is given by:

Choose CIN so that f-3dB is well below the lowest fre-

quency of interest. Use capacitors whose dielectrics

have low-voltage coefficients, such as tantalum or alu-

minum electrolytic. Capacitors with high-voltage coeffi-

cients, such as ceramics, may result in increased

distortion at low frequencies.

BIAS Capacitor

BIAS is the output of the internally generated DC bias volt-

age. The BIAS bypass capacitor, CBIAS, reduces power

supply and other noise sources at the common-mode

bias node. Bypass BIAS with a 1µF capacitor to GND.

Charge-Pump Capacitor Selection

Use capacitors with an ESR less than 100m

Ω for optimum

performance. Low-ESR ceramic capacitors minimize the

output resistance of the charge pump. Most surface-

mount ceramic capacitors satisfy the ESR requirement.

For best performance over the extended temperature

range, select capacitors with an X7R dielectric.

Flying Capacitor (C1)

The value of the flying capacitor (C1) affects the output

resistance of the charge pump. A C1 value that is too

small degrades the device’s ability to provide sufficient

current drive, which leads to a loss of output voltage.

Increasing the value of C1 reduces the charge-pump out-

put resistance to an extent. Above 1µF, the on-resistance

of the switches and the ESR of C1 and C2 dominate.

Output Holding Capacitor (C2)

The output capacitor value and ESR directly affect the

ripple at VSS. Increasing the value of C2 reduces output

ripple. Likewise, decreasing the ESR of C2 reduces both

ripple and output resistance. Lower capacitance values

can be used in systems with low maximum output power

levels. See the

Output Power vs. Load Resistance graph

in the

Typical Operating Characteristics.

PVDD Bulk Capacitor (C3)

In addition to the recommended PVDD bypass capaci-

tance, bulk capacitance equal to C3 should be used.

Place the bulk capacitor as close as possible to the device.

Supply Bypassing,

Layout, and Grounding

Proper layout and grounding are essential for optimum

performance. Use wide traces for the power-supply

inputs and amplifier outputs to minimize losses due to

parasitic trace resistance. Wide traces also aid in mov-

ing heat away from the package. Proper grounding

improves audio performance, minimizes crosstalk

between channels, and prevents any switching noise

from coupling into the audio signal. Connect PGND and

GND together at a single point on the PCB. Route all

traces that carry switching transients away from GND

and the traces/components in the audio signal path.

Connect the PVDD_ pins to a 2.7V to 5.5V source.

Bypass PVDD_ to PGND pin with a 1µF ceramic capac-

itor. Additional bulk capacitance should be used to pre-

vent power supply pumping. Bypass PVDD_ to the

PGND pin with a 1µF ceramic capacitor. Additional

bulk capacitance should be used to prevent power-

supply pumping. Place the bypass capacitors as close

as possible to the MAX9879.

Connect VDD to PVDD_. Bypass VDD to GND with a

1µF capacitor. Place the bypass capacitors as close as

possible to the MAX9879.

IN IN

−

RF SUSCEPTIBILITY

FREQUENCY (Hz)

10k

100

-130

-110

-90

-70

-50

-30

-10

-150

100k

THRESHOLD OF HEARING

MAX9879

NOISE FLOOR

Figure 14. MAX9879 Susceptibility to a GSM Cell Phone Radio

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